The ar71xx GPIO driver only uses 0x24 registers, all following GPIO
registers are using to control pinmux functions, which are not handles
by the GPIO driver but the generic Linux pinctrl driver.
For some SoC conflicting address ranges were defined for these (AR7240 &
AR9330).
Resolve these cases and align the address space of the GPIO controller
between all SoCs, as the used address space of the driver is identical
for all these.
Signed-off-by: David Bauer <mail@david-bauer.net>
Analysis done by Denis Kalashnikov:
It seems that some ROS versions on some routerboard models have this bug:
after silence boot (no output to uart, no beeps) beeper clicks when wireless traffic is.
https://forum.mikrotik.com/viewtopic.php?f=3&t=92269https://forum.mikrotik.com/viewtopic.php?t=63399
From these links:
1)
Hello, I have RB951G-2HnD and I noticed strange thing
when I loaded the device with some wireless traffic it
produced strange sound - like hissing, fizzing etc.
2)
Same problem still on 6.33, with silent boot enabled
I hear buzzing noise on wireless load.
3)
The sound is fixed in v5.19, it was a bug that caused beeper to make clicks.
It also got fixed in RouterOS:
* What's new in 5.19 (2012-Jul-16 10:51):
fix ticking sound on RB411UAHL;
* What's new in 6.38.3 (2017-Feb-07 09:52):
rb3011 - fixed noise from buzzer after silent boot;
I've checked with an oscilloscope that:
* When on the ssr beeper pin is 0,
on the beeper itself is 1 (~5V),
and when on the ssr beeper pin is 1,
on the beeper is 0
The beeper doesn't consume power,
so 1 should be a default/idle value for the ssr beeper pin).
* When there is wireless traffic (ping packets)
in the background and the beeper clicks, I see
pulses on the beeper itself,
but no pulses on the ssr beeper pin (Q5 pin of 74hc595).
When I manually toggle the ssr beeper pin I see pulses on both.
So, it is likely that the phantom beeper clicks are caused by the EMI.
Suggested-by: Denis Kalashnikov <denis281089@gmail.com>
Reviewed-by: Sergey Ryazanov <ryazanov.s.a@gmail.com>
Signed-off-by: Koen Vandeputte <koen.vandeputte@ncentric.com>
When the ltq_deu_vr9 kernel module is loaded, hostapd does not start any
more. It fails with this error message:
daemon.err hostapd: nl80211: kernel reports: key addition failed
daemon.err hostapd: Interface initialization failed
OpenWrt uses the standard Linux crypto API in the wifi drivers now
and this probably makes the system offload more crypto operations to
special hardware like the Lantiq DEU. There is probably a bug in the DEU
and these operations fail and then hostapd does not start the interface.
Do not include the Lantiq DEU by default any more.
Fixes: FS#3901
Fixes: 53b6783907 ("mac80211: remove patches stripping down crypto support")
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Acked-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Tested-by: Notupus <notpp46@gmail.com>
2 small fix for the dedicated cpufreq driver:
- Fix index wrongly used as the current cpu
- Exit early if a bad freq is detected. In the current state the freq
is applied anyway even with invalid state.
Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
With the new implementation of the dedicated cpufreq driver,
the 1.4 Ghz was only dropped and not added to the ipq8065 SoC.
Fix this to improve performance.
Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
The new cpufreq dedicated driver changed the node structure
on how the cache should be defined in the dts. The 5.4 dtsi addition
patch has not been updated to follow the new implementation.
Fix this to restore correct cache scaling and restore any performance
regression.
Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
This commit adds support for the Teltonika RUT230 v1, a Atheros AR9331
based router with a Quectel UC20 UMTS modem.
Hardware
--------
Atheros AR9331
16 MB SPI-NOR XTX XT25F128B
64M DDR2 memory
Atheros AR9331 1T1R 802.11bgn Wireless
Boootloader: pepe2k U-Boot mod
Hardware-Revision
-----------------
There are two board revisions of the RUT230, a v0 and v1.
A HW version is silkscreened on the top of the PCBs front side as well
as shown in the Teltonika UI. However, this looks to be a different
identifier, as the GPl dump shows this silkscreened / UI shown version
are internally treated identically.
Th following mapping has been obtained from the latest GPl dump.
HW Ver 01 - 04 --> v0
HW Ver > 05 --> v1
My board was a HW Ver 09 and is treated as a v1.
Installation
------------
While attaching power, hold down the reset button and release it after
the signal LEDs flashed 3 times.
Attach your Computer with the devices LAN port and assign yourself the
IPv4 address 192.168.1.10/24. Open a web browser, navigate to
192.168.1.1. Upload the OpenWrt factory image.
The device will install OpenWrt and automatically reboots afterwards.
You can use the smae procedure with the stock firmware to return back to
the vendor firmware.
Signed-off-by: David Bauer <mail@david-bauer.net>
The beeper is currently not fully functional and has also
been removed from DTS.
Also remove the dependency for the gpio-beeper module.
Fixes: 695a1cd53c ("ath79: add support for MikroTik RouterBOARD 912UAG-2HPnD")
Signed-off-by: Koen Vandeputte <koen.vandeputte@ncentric.com>
* With kernel 5.4.128, ran: make kernel_menuconfig CONFIG_TARGET=generic
* Manually added back CONFIG_LEDS_TRIGGER_DISK=y so as not to revert
f93fcf8923 ("ipq806x: enable disk-activity LED trigger")
Signed-off-by: John Audia <graysky@archlinux.us>
[minor commit title/message adjustments]
Signed-off-by: Adrian Schmutzler <freifunk@adrianschmutzler.de>
Though not strictly necessary, add the closing symbol to make the
job easier for future developers editing this file.
Signed-off-by: Adrian Schmutzler <freifunk@adrianschmutzler.de>
Hardware
--------
MediaTek MT7621 SoC
256M DDR3
16MB BoHong SPI-NOR
MediaTek MT7905+7975 2x2T2R DBDC bgnax / acax
RGB LED
WPS + RESET Button
UART on compute module (silkscreened / 115200n8)
The router itself is just a board with Power / USB / RJ-45 connectors
and DC/DC converters. The SoC and WiFi components are on a
daughterboard which connect using two M.2 connectors.
The compute module has the model number "T-CB1800K-DM2 V02" printed on
it. The main baord has "T-MB5EU V01" printed on it. This information
might be useful, as it's highly likely either of these two will be
reused in similar designs.
The router itself is sold as Tenbay T-MB5EU directly from the OEM as
well as "KuWFI AX1800 Smart WiFi 6 Eouter" on Amazon.de for ~50€ in a
slightly different case.
Installation
------------
A Tool for creating a factory image for the Vendor Web Interface can be
found here: https://github.com/blocktrron/t-mb5eu-v01-factory-creator/
As the OEM Firmware is just a modified LEDE 17.01, you can also access
failsafe mode via UART while the OS boots, by connecting to UART
and pressing "f" when prompted. The Router is reachable at
192.168.1.1 via root without password.
Transfer the OpenWrt sysupgrade image via scp and apply with sysupgrade
using the -n and -F flags.
Alternatively, the board can be flashed by attaching to the UART
console, interrupting the boot process by keeping "0" pressed while
attaching power.
Serve the OpenWrt initramfs using a TFTP server with address
192.168.1.66. Rename the initramfs to ax1800.bin.
Attach your TFTP server to one of the LAN ports. Execute the following
commands.
$ setenv ipaddr 192.168.1.67
$ setenv serverip 192.168.1.66
$ tftpboot 0x84000000 ax1800.bin
$ bootm
Wait for the device to boot. Then transfer the OpenWrt sysupgrade image
to the device using SCP and apply sysupgrade.
Signed-off-by: David Bauer <mail@david-bauer.net>
This adds a driver for the AW9523 I2C GPIO expander.
This driver is required to make LEDs as well as buttons on the Tenbay
T-MB5EU-V01 work.
This driver already had several upstream iterations. I'm working to
push this driver to mainline.
Ref: https://patchwork.ozlabs.org/project/linux-gpio/list/?series=226287
Signed-off-by: David Bauer <mail@david-bauer.net>
It was reported AR8033 did not work in fiber operation mode on the ER-X.
While the earlier attempt of fixing this mitigated the issue of 1000
Base-X link mode not being supported, it also switched to the copper
page, breaking fiber operation altogether.
Extend the hack adding fiber operation so it does not switch to the
copper page. Also remove the part where the supported link mode bit for
1000 Base-X is removed, as this is required for fiber operation.
Signed-off-by: David Bauer <mail@david-bauer.net>
AR8031/AR8033 have different status registers for copper
and fiber operation. However, the extended status register
is the same for both operation modes.
As a result of that, ESTATUS_1000_XFULL is set to 1 even when
operating in copper TP mode.
Remove this mode from the supported link modes, as this driver
currently only supports copper operation.
Signed-off-by: David Bauer <mail@david-bauer.net>
Enable the XRX200 PMAC, GSWIP DSA tag and GSIP DSA drivers in the 5.4
kernel config. Update the existing vr9_*.dts{,i} to use the new
Ethernet and switch drivers. Drop the swconfig package from the xrx200
target because swconfig doesn't manage DSA based switches.
The new /etc/config/network format for the DSA driver is not compatible
with the old (swconfig) based one. Show a message during sysupgrade
notifying users about this change and asking them to start with a fresh
config (or forcefully update and then migrate the config manually).
Failsafe mode can now automatically bring up the first lan interface
based on board.json including DSA based setups. Drop
05_set_preinit_iface_lantiq from the xRX200 sub-target as this is not
needed anymore. For now we are keeping it for the ase, xway and
xway_legacy until there's some confirmation that it can be dropped from
there as well.
While here, some boards also receive minor fixups:
- Use LAN1 as LAN1 (according to a photo this port can also be
configured as WAN) on the Buffalo WBMR-300HPD. This makes it easier to
read the port mapping because otherwise we would have LAN{2,3,4} and
WAN (which was the case for the non-DSA version previously).
- vr9_avm_fritz3390.dts: move the "gpio" comment from port 0 and 1 to
their corresponding PHYs
- vr9_tplink_vr200.dtsi: move the "gpio" comment from port 0 to PHY 0
- vr9_tplink_tdw89x0.dtsi: move the "gpio" comment from port 0 to PHY 0
Acked-by: Aleksander Jan Bajkowski <A.Bajkowski@stud.elka.pw.edu.pl>
Tested-by: Notupus <notpp46@googlemail.com> # TD-W9980/DM200/FRITZ 7430
Tested-by: Martin Schiller <ms@dev.tdt.de> # tested on TDT VR2020
Tested-by: Martin Schiller <ms@dev.tdt.de> # tested on TP-Link TD-W8980B
Tested-by: Martin Schiller <ms@dev.tdt.de> # tested on ZyXEL P-2812HNU-F1
Tested-by: Daniel Kestrel <kestrel1974@t-online.de> # tested on Fritzbox 7490
Tested-by: Daniel Kestrel <kestrel1974@t-online.de> # tested on Fritzbox 3490
Tested-by: @jospezial <jospezial@gmx.de> # tested on VGV7510KW22 (o2 Box 6431)
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Manually rebased:
bcm27xx/patches-5.4/950-0089-cgroup-Disable-cgroup-memory-by-default.patch
All other patches automatically rebased.
Signed-off-by: John Audia <graysky@archlinux.us>
Ensure the esw is initialized before the ethernet device is sending
packets. Further implement carrier detection similar to mt7620.
If any port has a link, the ethernet device will detect a carrier.
Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
For rt3050 the switch needs to be initialized before the ethernet start sending
packets. Allow switch_init to return -EPROBE_DEFER.
Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
The dts defines the reset fe for all architectures. However
the soc code used direct register access of the reset controller.
Replace the custom soc reset with a generic fe_reset_fe().
Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
The fe_reset function direct access the reset controller instead
using the reset controller api. In preparation to use the
reset controller.
Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
In the new kernel version 5.X,reboot will fail.
When SOC is reset, flash has not exited the 4-byte address mode,
which causes the operation mode mismatch of flash during boot.Add
broken-flash-reset to make flash exit 4-byte address mode before
SOC reset
Signed-off-by: Liu Yu <f78fk@live.com>
Without this definition ethernet led can work as usual, but it's better to
re-add it. Relying on default values may cause uncontrollable factors.
Fixes: 882a6116d3 ("ramips: improve pinctrl for Youku YK-L1")
Signed-off-by: Shiji Yang <yangshiji66@qq.com>
These boards have AR8327 or QCA8337 external ethernet switch.
The SOC also has it's own internal switch
where VLAN is now enabled by default.
Changes to preinit caused all switches to have VLANs enabled by default
even if they are not configured with a topology in uci_defaults
(see commit f017f617ae)
When both internal and external switches have VLANs,
and the external switch has both LAN and WAN,
the TX traffic from the SOC cannot flow to the tagged port on the external switch
because the VLAN IDs are not matching.
So disable the internal switch VLANs by default on these boards.
Also, add a topology for the internal switch,
so that on LuCI there is not an "unknown topology" warning.
In theory, it may be possible to have LAN ports on both switches
through internal and external PHYs, but there are no known boards that have this.
Signed-off-by: Michael Pratt <mcpratt@pm.me>
Define and use some missing macros,
and use them instead of BIT() or numbers for more readable code.
Add comment for a bit change that seems unrelated to ethernet
but is actually needed (PCIe Root Complex mode).
Remove unknown and unused macro RST_CTRL_MCM
(probably from MT7621 / MT7622)
This is the last of a series of fixes, so bump version.
Signed-off-by: Michael Pratt <mcpratt@pm.me>
the register bits for TX delay and RX delay are opposites:
when TX delay bit is set, delay is enabled
when RX delay bit is set, delay is disabled
So, when both bits are unset, it is RX delay
and when both bits are set, it is TX delay
Note: TXID is the default RGMII mode of the SOC
Fixes: 5410a8e295 ("ramips: mt7620: add rgmii delays support")
Signed-off-by: Michael Pratt <mcpratt@pm.me>
Add back the register write to disable internal PHYs
as a separate option in the code that can be set using a DTS property.
Set the option to true by default
when an external mt7530 switch is identified.
This makes the driver more in sync with original SDK code
while keeping the lines separated into different options
to accommodate any board with any PHY layout.
Signed-off-by: Michael Pratt <mcpratt@pm.me>
The function mt7620_mdio_mode is only called once
and both the function and mdio_mode block have been named incorrectly,
leading to confusion and useless commits.
These lines in the mdio_mode block of mt7620_hw_init
are only intended for boards with an external mt7530 switch.
(see commit 194ca6127e)
Therefore, move lines from mdio_mode to the place in soc_mt7620.c
where the type of mt7530 switch is identified,
and move lines from mt7620_mdio_mode to a main function.
mt7620_mdio_mode was called from mt7620_gsw_init
where the priv struct is available,
so the lines must stay in mt7620_gsw_init function.
In order to keep things as simple as possible,
keep the DTS property related function calls together,
by moving them from mt7620_gsw_probe to init.
Remove the now useless DTS properties and extra phy nodes.
Fixes: 5a6229a93d ("ramips: remove superfluous & confusing DT binding")
Fixes: b85fe43ec8 ("ramips: mt7620: add force use of mdio-mode")
Signed-off-by: Michael Pratt <mcpratt@pm.me>
Set the PHY base address to 12 for mt7530 and 8 for others,
which is based on the default setting for some devices
from printing the register with the following command
after it is written to by uboot during the boot cycle.
`md 0x10117014 1`
PHY_BASE option only uses 5 bits of the register,
bits 16 to 20, so use 8-bit integer type.
Set the option using the DTS property mediatek,ephy-base
and create the gsw node if missing.
Also, added a kernel message to display the EPHY base address.
Note:
If anything is written to a PHY address that is greater than 1 hex char (greater than 0xf)
then there is adverse effects with Atheros switches.
Signed-off-by: Michael Pratt <mcpratt@pm.me>
When the new variable ephy_base was introduced,
it was not applied to the if block for mdio_mode.
The first line in the mdio_mode if block
sets the EPHY base address to 12 in the SOC by writing a register,
but the corresponding variable in the driver
was still set to the default of 0.
This causes subsequent lines that write registers with the function
_mt7620_mii_write
to write to PHY addresses 0 through 4
while internal PHYs have been moved to addresses 12 through 16.
All of these lines are intended only for PHYs on the SOC internal switch,
however, they are being written to external ethernet switches
if they exist at those PHY addresses 0 through 4.
This causes some ethernet ports to be broken on boards with AR8327 or QCA8337 switch.
Other suggested fixes move those lines to the else block of mdio_mode,
but removing the else block completely also fixes it.
Therefore, move the lines to the mt7620_hw_init function main block,
and have only one instance of the function mtk_switch_w32
for writing the register with the EPHY base address.
In theory, this also allows for boards that have both external switches
and internal PHYs that lead to ethernet ports to be supported.
Fixes: 391df37829 ("ramips: mt7620: add EPHY base mdio address changing possibility")
Signed-off-by: Michael Pratt <mcpratt@pm.me>
A workaround was added to the switch driver
to set SOC port 4 as an RGMII GMAC interface
based on the DTS property mediatek,port4-gmac.
(previously mediatek,port4)
However, the ethernet driver already does this,
but is being blocked by a return statement
whenever the phy-handle and fixed-link properties
are both missing from nodes that define the port properties.
Revert the workaround, so that both the switch driver
and ethernet driver are not doing the same thing
and move the phy-handle related lines down
so nothing is ending the function prematurely.
While at it, clean up kernel messages
and delete useless return statements.
Fixes: f6d81e2fa1 ("mt7620: gsw: make IntPHY and ExtPHY share mdio addr 4 possible")
Signed-off-by: Michael Pratt <mcpratt@pm.me>
These nodes are used for configuring a GMAC interface
and for defining external PHYs to be accessed with MDIO.
None of this is possible on MT7620N, only MT7620A,
so remove them from all MT7620N DTS.
When the mdio-bus node is missing, the driver returns -NODEV
which causes the internal switch to not initialize.
Replace that return so that everything works without the DTS node.
Also, an extra kernel message to indicate for all error conditions
that mdio-bus is disabled.
Fixes: d482356322 ("ramips: mt7620n: add mdio node and disable port4 by default")
Fixes: aa5014dd1a ("ramips: mt7620n: enable port 4 as EPHY by default")
Signed-off-by: Michael Pratt <mcpratt@pm.me>
There are only 2 options in the driver
for the function of mt7620 internal switch port 4:
EPHY mode (RJ-45, internal PHY)
GMAC mode (RGMII, external PHY)
Let the DTS property be boolean instead of string
where EPHY mode is the default.
Fix how the properties are written
for all DTS that use them,
and add missing nodes where applicable,
and remove useless nodes,
and minor DTS formatting.
Signed-off-by: Michael Pratt <mcpratt@pm.me>
The RTL8380-RTL9300 switches only forward packets when VLAN ID 1 is
configured. Do not use the standard failsafe configuration for DSA
accessing the default port directly, but configure a switch on the lan1
interface instead.
This will add the VLAN ID 1 configuration to the switch:
$ bridge vlan show
port vlan-id
lan1 1 PVID Egress Untagged
switch 1 PVID Egress Untagged
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Without this patch we have to manually bring up the CPU interface in
failsafe mode.
This was backported from kernel 5.12.
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Tested-by: Rafał Miłecki <rafal@milecki.pl>
These are the latest patches that just landed upstream for 5.13, will be
backported by Greg into 5.10 (because of stable@), and are now in the
5.4 backport branch of wireguard: https://git.zx2c4.com/wireguard-linux/log/?h=backport-5.4.y
Cc: Ilya Lipnitskiy <ilya.lipnitskiy@gmail.com>
Signed-off-by: Jason A. Donenfeld <Jason@zx2c4.com>
Tested-by: Stijn Segers <foss@volatilesystems.org>
Fixes the buffer and packet length calculations for Ethernet TX on
the RTL8380 SoC when CRC calculation offload is enabled.
CRC-offload is always done by the SoC, but additional CRC
calculation was previously done also by the kernel.
It also fixes detection of the DSA tag for packets on RTL8390
SoCs for ports > 28.
v2 has correct whitespace
Signed-off-by: Birger Koblitz <mail@birger-koblitz.de>
Currently, the option to disable subpage writing is only set
when a HW ECC engine is used.
Some boards lack a HW ECC engine and use software for that.
In this case, this NAND option does not get set when the NAND chip
does not support it, resulting in mounting errors.
Move the setting of this option to a generic init location so it
gets set for all types where required.
While at it, also OR the option instead of just setting it
so we don't overwrite potential flags being set somewhere else.
Before:
[ 1.681273] UBI: auto-attach mtd2
[ 1.684669] ubi0: attaching mtd2
[ 1.688877] ubi0 error: validate_ec_hdr: bad VID header offset 2048, expected 512
[ 1.696469] ubi0 error: validate_ec_hdr: bad EC header
[ 1.701712] Erase counter header dump:
[ 1.705512] magic 0x55424923
[ 1.709322] version 1
[ 1.712330] ec 1
[ 1.715331] vid_hdr_offset 2048
[ 1.718610] data_offset 4096
[ 1.721880] image_seq 1462320675
[ 1.725680] hdr_crc 0x12255a15
After:
1.680917] UBI: auto-attach mtd2
[ 1.684308] ubi0: attaching mtd2
[ 2.954504] random: crng init done
[ 3.142813] ubi0: scanning is finished
[ 3.163455] ubi0: attached mtd2 (name "ubi", size 124 MiB)
[ 3.169069] ubi0: PEB size: 131072 bytes (128 KiB), LEB size: 126976 bytes
[ 3.176037] ubi0: min./max. I/O unit sizes: 2048/2048, sub-page size 2048
[ 3.182942] ubi0: VID header offset: 2048 (aligned 2048), data offset: 4096
[ 3.190013] ubi0: good PEBs: 992, bad PEBs: 0, corrupted PEBs: 0
[ 3.196102] ubi0: user volume: 3, internal volumes: 1, max. volumes count: 128
[ 3.203434] ubi0: max/mean erase counter: 2/0, WL threshold: 4096, image sequence number: 1462320675
[ 3.212700] ubi0: available PEBs: 0, total reserved PEBs: 992, PEBs reserved for bad PEB handling: 20
[ 3.222124] ubi0: background thread "ubi_bgt0d" started, PID 317
[ 3.230246] block ubiblock0_1: created from ubi0:1(rootfs)
[ 3.235819] ubiblock: device ubiblock0_1 (rootfs) set to be root filesystem
[ 3.256830] VFS: Mounted root (squashfs filesystem) readonly on device 254:0.
Signed-off-by: Koen Vandeputte <koen.vandeputte@ncentric.com>
This board has been supported in the ar71xx.
Links:
* https://mikrotik.com/product/RB912UAG-2HPnD
* https://openwrt.org/toh/hwdata/mikrotik/mikrotik_rb912uag-2hpnd
This also supports the 5GHz flavour of the board.
Hardware:
* SoC: Atheros AR9342,
* RAM: DDR 64MB,
* SPI NOR: 64KB,
* NAND: 128MB,
* Ethernet: x1 10/100/1000 port with passive POE in,
* Wi-Fi: 802.11 b/g/n,
* PCIe,
* USB: 2.0 EHCI controller, connected to mPCIe slot and a Type-A
port -- both can be used for LTE modem, but only one can be
used at any time.
* LEDs: 5 general purpose LEDs (led1..led5), power LED, user LED,
Ethernet phy LED,
* Button,
* Beeper.
Not working:
* Button: it shares gpio line 15 with NAND ALE and NAND IO7,
and current drivers doesn't easily support this configuration,
* Beeper: it is connected to bit 5 of a serial shift register
(tested with sysfs led trigger timer). But kmod-gpio-beeper
doesn't work -- we left this as is for now.
Flashing:
* Use the RouterBOARD Reset button to enable TFTP netboot,
boot kernel and initramfs and then perform sysupgrade.
* From ar71xx OpenWrt firmware run:
$ sysupgrade -F /tmp/<sysupgrade.bin>
For more info see: https://openwrt.org/toh/mikrotik/common.
Co-Developed-by: Koen Vandeputte <koen.vandeputte@citymesh.com>
Reviewed-by: Sergey Ryazanov <ryazanov.s.a@gmail.com>
Signed-off-by: Denis Kalashnikov <denis281089@gmail.com>
Main part is copied from ar71xx original driver rb91x_nand
written by Gabor Juhos <juhosg@openwrt.org>.
What is done:
* Support of kernel 5.4 and 5.10,
* DTS support,
* New gpio API (gpiod_*) support.
Reviewed-by: Sergey Ryazanov <ryazanov.s.a@gmail.com>
Signed-off-by: Denis Kalashnikov <denis281089@gmail.com>
This is a slighty modified version of ar71xx gpio-latch driver
written by Gabor Juhos <juhosg@openwrt.org>.
Changes:
* DTS support,
* New gpio API (gpiod_*).
Reviewed-by: Sergey Ryazanov <ryazanov.s.a@gmail.com>
Signed-off-by: Denis Kalashnikov <denis281089@gmail.com>
David Bauer
Adrian Schmutzler