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ramips: mt7620: move mt7620_mdio_mode() to ethernet driver 

The function mt7620_mdio_mode is only called once
and both the function and mdio_mode block have been named incorrectly,
leading to confusion and useless commits.

These lines in the mdio_mode block of mt7620_hw_init
are only intended for boards with an external mt7530 switch.
(see commit 194ca6127e)

Therefore, move lines from mdio_mode to the place in soc_mt7620.c
where the type of mt7530 switch is identified,
and move lines from mt7620_mdio_mode to a main function.

mt7620_mdio_mode was called from mt7620_gsw_init
where the priv struct is available,
so the lines must stay in mt7620_gsw_init function.

In order to keep things as simple as possible,
keep the DTS property related function calls together,
by moving them from mt7620_gsw_probe to init.

Remove the now useless DTS properties and extra phy nodes.

Fixes: 5a6229a93d ("ramips: remove superfluous & confusing DT binding")
Fixes: b85fe43ec8 ("ramips: mt7620: add force use of mdio-mode")
Signed-off-by: Michael Pratt <mcpratt@pm.me>
This commit is contained in:
Michael Pratt 2021-05-30 02:02:47 -04:00 committed by Chuanhong Guo
parent 0976b6c426
commit 6972e498d3
5 changed files with 38 additions and 74 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
target/linux/ramips/dts/mt7620a_edimax_ew-747x.dtsi
View File

@ -155,8 +155,6 @@
mtd-mac-address = <&factory 0x4>;
mediatek,mdio-mode = <1>;
phy-reset-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
phy-reset-duration = <30>;

1
target/linux/ramips/dts/mt7620a_engenius_esr600.dts
View File

@ -144,7 +144,6 @@
mdio-bus {
status = "okay";
mediatek,mdio-mode;
ethernet-phy@0 {
reg = <0>;

23
target/linux/ramips/dts/mt7620a_lava_lr-25g001.dts
View File

@ -115,9 +115,8 @@
mdio-bus {
status = "okay";
mediatek,mdio-mode = <1>;
phy0: ethernet-phy@0 {
ethernet-phy@0 {
reg = <0>;
phy-mode = "rgmii";
qca,ar8327-initvals = <
@ -127,26 +126,6 @@
0x94 0x00000000 /* PORT6_STATUS */
>;
};
phy1: ethernet-phy@1 {
reg = <1>;
phy-mode = "rgmii";
};
phy2: ethernet-phy@2 {
reg = <2>;
phy-mode = "rgmii";
};
phy3: ethernet-phy@3 {
reg = <3>;
phy-mode = "rgmii";
};
phy4: ethernet-phy@4 {
reg = <4>;
phy-mode = "rgmii";
};
};
};

71
target/linux/ramips/files/drivers/net/ethernet/ralink/gsw_mt7620.c
View File

@ -61,31 +61,7 @@ static irqreturn_t gsw_interrupt_mt7620(int irq, void *_priv)
return IRQ_HANDLED;
}
static int mt7620_mdio_mode(struct device_node *eth_node)
{
struct device_node *phy_node, *mdiobus_node;
const __be32 *id;
int ret = 0;
mdiobus_node = of_get_child_by_name(eth_node, "mdio-bus");
if (mdiobus_node) {
if (of_property_read_bool(mdiobus_node, "mediatek,mdio-mode"))
ret = 1;
for_each_child_of_node(mdiobus_node, phy_node) {
id = of_get_property(phy_node, "reg", NULL);
if (id && (be32_to_cpu(*id) == 0x1f))
ret = 1;
}
of_node_put(mdiobus_node);
}
return ret;
}
static void mt7620_hw_init(struct mt7620_gsw *gsw, int mdio_mode)
static void mt7620_hw_init(struct mt7620_gsw *gsw)
{
u32 i;
u32 val;
@ -97,20 +73,6 @@ static void mt7620_hw_init(struct mt7620_gsw *gsw, int mdio_mode)
/* Enable MIB stats */
mtk_switch_w32(gsw, mtk_switch_r32(gsw, GSW_REG_MIB_CNT_EN) | (1 << 1), GSW_REG_MIB_CNT_EN);
if (mdio_mode) {
/* set MT7530 central align */
val = mt7530_mdio_r32(gsw, 0x7830);
val &= ~BIT(0);
val |= BIT(1);
mt7530_mdio_w32(gsw, 0x7830, val);
val = mt7530_mdio_r32(gsw, 0x7a40);
val &= ~BIT(30);
mt7530_mdio_w32(gsw, 0x7a40, val);
mt7530_mdio_w32(gsw, 0x7a78, 0x855);
}
if (gsw->ephy_base) {
mtk_switch_w32(gsw, mtk_switch_r32(gsw, GSW_REG_GPC1) |
(gsw->ephy_base << 16),
@ -215,9 +177,13 @@ MODULE_DEVICE_TABLE(of, mediatek_gsw_match);
int mtk_gsw_init(struct fe_priv *priv)
{
struct device_node *eth_node = priv->dev->of_node;
struct device_node *phy_node, *mdiobus_node;
struct device_node *np = priv->switch_np;
struct platform_device *pdev = of_find_device_by_node(np);
struct mt7620_gsw *gsw;
const __be32 *id;
u8 val;
if (!pdev)
return -ENODEV;
@ -228,7 +194,23 @@ int mtk_gsw_init(struct fe_priv *priv)
gsw = platform_get_drvdata(pdev);
priv->soc->swpriv = gsw;
mt7620_hw_init(gsw, mt7620_mdio_mode(priv->dev->of_node));
mdiobus_node = of_get_child_by_name(eth_node, "mdio-bus");
if (mdiobus_node) {
for_each_child_of_node(mdiobus_node, phy_node) {
id = of_get_property(phy_node, "reg", NULL);
if (id && (be32_to_cpu(*id) == 0x1f))
of_node_put(mdiobus_node);
}
}
gsw->port4_ephy = !of_property_read_bool(np, "mediatek,port4-gmac");
if (of_property_read_u8(np, "mediatek,ephy-base", &val) == 0)
gsw->ephy_base = val;
else
gsw->ephy_base = 0;
mt7620_hw_init(gsw);
if (gsw->irq) {
request_irq(gsw->irq, gsw_interrupt_mt7620, 0,
@ -243,8 +225,6 @@ static int mt7620_gsw_probe(struct platform_device *pdev)
{
struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
struct mt7620_gsw *gsw;
struct device_node *np = pdev->dev.of_node;
u8 val;
gsw = devm_kzalloc(&pdev->dev, sizeof(struct mt7620_gsw), GFP_KERNEL);
if (!gsw)
@ -256,13 +236,6 @@ static int mt7620_gsw_probe(struct platform_device *pdev)
gsw->dev = &pdev->dev;
gsw->port4_ephy = !of_property_read_bool(np, "mediatek,port4-gmac");
if (of_property_read_u8(np, "mediatek,ephy-base", &val) == 0)
gsw->ephy_base = val;
else
gsw->ephy_base = 0;
gsw->irq = platform_get_irq(pdev, 0);
platform_set_drvdata(pdev, gsw);

15
target/linux/ramips/files/drivers/net/ethernet/ralink/soc_mt7620.c
View File

@ -82,11 +82,26 @@ static const u16 mt7620_reg_table[FE_REG_COUNT] = {
static int mt7620_gsw_config(struct fe_priv *priv)
{
struct mt7620_gsw *gsw = (struct mt7620_gsw *) priv->soc->swpriv;
u32 val;
/* is the mt7530 internal or external */
if (priv->mii_bus && mdiobus_get_phy(priv->mii_bus, 0x1f)) {
mt7530_probe(priv->dev, gsw->base, NULL, 0);
mt7530_probe(priv->dev, NULL, priv->mii_bus, 1);
/* magic values from original SDK */
val = mt7530_mdio_r32(gsw, 0x7830);
val &= ~BIT(0);
val |= BIT(1);
mt7530_mdio_w32(gsw, 0x7830, val);
val = mt7530_mdio_r32(gsw, 0x7a40);
val &= ~BIT(30);
mt7530_mdio_w32(gsw, 0x7a40, val);
mt7530_mdio_w32(gsw, 0x7a78, 0x855);
pr_info("mt7530: mdio central align\n");
} else {
mt7530_probe(priv->dev, gsw->base, NULL, 1);
}