ramips: mt7620: simplify DTS properties for GMAC

There are only 2 options in the driver
for the function of mt7620 internal switch port 4:

  EPHY mode (RJ-45, internal PHY)
  GMAC mode (RGMII, external PHY)

Let the DTS property be boolean instead of string
where EPHY mode is the default.

Fix how the properties are written
for all DTS that use them,
and add missing nodes where applicable,
and remove useless nodes,
and minor DTS formatting.

Signed-off-by: Michael Pratt <mcpratt@pm.me>
This commit is contained in:
Michael Pratt 2021-03-31 16:09:37 -04:00 committed by Chuanhong Guo
parent fe6b9b0588
commit 953bfe2eb3
41 changed files with 23 additions and 125 deletions

View File

@ -72,10 +72,6 @@
status = "okay";
};
&gsw {
mediatek,port4 = "ephy";
};
&ohci {
status = "okay";
};

View File

@ -141,10 +141,6 @@
status = "okay";
};
&gsw {
mediatek,port4 = "ephy";
};
&i2c {
status = "okay";
};

View File

@ -114,10 +114,6 @@
status = "okay";
};
&gsw {
mediatek,port4 = "ephy";
};
&ohci {
status = "okay";
};

View File

@ -153,8 +153,7 @@
};
};
&gsw {
mediatek,port4 = "ephy";
&ethernet {
pinctrl-names = "default";
pinctrl-0 = <&ephy_pins>;
};

View File

@ -157,10 +157,6 @@
};
};
&gsw {
mediatek,port4 = "ephy";
};
&wmac {
ralink,mtd-eeprom = <&factory 0x0>;
};

View File

@ -144,10 +144,6 @@
mediatek,portmap = "llllw";
};
&gsw {
mediatek,port4 = "ephy";
};
&wmac {
ralink,mtd-eeprom = <&factory 0x0>;
pinctrl-names = "default";

View File

@ -144,10 +144,6 @@
mediatek,portmap = "llllw";
};
&gsw {
mediatek,port4 = "ephy";
};
&wmac {
ralink,mtd-eeprom = <&factory 0x0>;
};

View File

@ -132,10 +132,6 @@
mediatek,portmap = "llllw";
};
&gsw {
mediatek,port4 = "ephy";
};
&gpio2 {
status = "okay";
};

View File

@ -171,10 +171,6 @@
mtd-mac-address = <&factory 0x4>;
};
&gsw {
ralink,port4 = "ephy";
};
&wmac {
ralink,mtd-eeprom = <&factory 0x0>;
pinctrl-names = "default";

View File

@ -120,10 +120,6 @@
};
};
&gsw {
mediatek,port4 = "ephy";
};
&state_default {
default {
groups = "i2c", "uartf";

View File

@ -185,5 +185,5 @@
};
&gsw {
mediatek,port4 = "gmac";
mediatek,port4-gmac;
};

View File

@ -173,6 +173,6 @@
};
&gsw {
mediatek,port4 = "gmac";
mediatek,port4-gmac;
mediatek,ephy-base-address = /bits/ 16 < 2 >;
};

View File

@ -135,7 +135,7 @@
};
&gsw {
mediatek,port4 = "gmac";
mediatek,port4-gmac;
};
&pcie {

View File

@ -177,10 +177,6 @@
};
};
&gsw {
mediatek,port4 = "gmac";
};
&wmac {
ralink,mtd-eeprom = <&factory 0x0>;
};

View File

@ -169,10 +169,6 @@
};
};
&gsw {
mediatek,port4 = "gmac";
};
&wmac {
ralink,mtd-eeprom = <&factory 0x0>;
};

View File

@ -201,10 +201,6 @@
};
};
&gsw {
mediatek,port5 = "gmac";
};
&wmac {
ralink,mtd-eeprom = <&factory 0x0>;
};

View File

@ -155,7 +155,7 @@
0x7c 0x0000007e /* PORT0 STATUS */
0x0c 0x05600000 /* PORT6 PAD MODE CTRL */
0x94 0x0000007e /* PORT6 STATUS */
>;
>;
};
};
};

View File

@ -136,7 +136,7 @@
};
&gsw {
mediatek,port4 = "gmac";
mediatek,port4-gmac;
};
&wmac {

View File

@ -149,6 +149,10 @@
};
};
&gsw {
mediatek,port4-gmac;
};
&wmac {
ralink,mtd-eeprom = <&factory 0x0>;
};

View File

@ -111,5 +111,5 @@
};
&gsw {
mediatek,port4 = "gmac";
mediatek,port4-gmac;
};

View File

@ -144,10 +144,6 @@
};
};
&gsw {
mediatek,port4 = "gmac";
};
&wmac {
ralink,mtd-eeprom = <&factory 0x0>;
};

View File

@ -103,10 +103,6 @@
mediatek,portmap = "llllw";
};
&gsw {
mediatek,port4 = "ephy";
};
&wmac {
ralink,mtd-eeprom = <&factory 0x0>;
};

View File

@ -122,10 +122,6 @@
mediatek,portmap = "llllw";
};
&gsw {
ralink,port4 = "ephy";
};
&sdhci {
status = "okay";
};

View File

@ -94,10 +94,6 @@
mediatek,portmap = "llllw";
};
&gsw {
mediatek,port4 = "ephy";
};
&wmac {
ralink,mtd-eeprom = <&factory 0x0>;
};

View File

@ -114,10 +114,6 @@
mediatek,portmap = "llllw";
};
&gsw {
mediatek,port4 = "ephy";
};
&wmac {
ralink,mtd-eeprom = <&factory 0x0>;
};

View File

@ -105,7 +105,7 @@
};
&gsw {
mediatek,port4 = "gmac";
mediatek,port4-gmac;
};
&sdhci {

View File

@ -99,10 +99,6 @@
};
};
&gsw {
mediatek,port4 = "gmac";
};
&pcie {
status = "okay";
};

View File

@ -71,10 +71,6 @@
mediatek,portmap = "llllw";
};
&gsw {
mediatek,port4 = "ephy";
};
&sdhci {
status = "okay";
};

View File

@ -99,7 +99,7 @@
};
&gsw {
mediatek,port4 = "gmac";
mediatek,port4-gmac;
};
&pcie {

View File

@ -166,7 +166,7 @@
};
&gsw {
mediatek,port4 = "gmac";
mediatek,port4-gmac;
};
&ehci {

View File

@ -178,10 +178,6 @@
status = "okay";
};
&gsw {
mediatek,port4 = "ephy";
};
&wmac {
ralink,mtd-eeprom = <&radio 0x0>;
};

View File

@ -105,10 +105,6 @@
status = "okay";
};
&gsw {
mediatek,port4 = "ephy";
};
&wmac {
ralink,mtd-eeprom = <&radio 0x0>;
};

View File

@ -61,7 +61,7 @@
};
&gsw {
mediatek,port4 = "gmac";
mediatek,port4-gmac;
};
&ethernet {

View File

@ -195,7 +195,7 @@
};
&gsw {
mediatek,port4 = "gmac";
mediatek,port4-gmac;
};
&wmac {

View File

@ -141,10 +141,6 @@
mediatek,portmap = "llllw";
};
&gsw {
ralink,port4 = "ephy";
};
&wmac {
ralink,mtd-eeprom = <&factory 0x0>;
};

View File

@ -111,7 +111,3 @@
&ohci {
status = "okay";
};
&gsw {
mediatek,port4 = "ephy";
};

View File

@ -157,7 +157,7 @@
};
&gsw {
mediatek,port4 = "gmac";
mediatek,port4-gmac;
};
&wmac {

View File

@ -347,7 +347,6 @@
interrupt-parent = <&intc>;
interrupts = <17>;
mediatek,port4 = "ephy";
};
ehci: ehci@101c0000 {

View File

@ -40,7 +40,7 @@ static irqreturn_t gsw_interrupt_mt7620(int irq, void *_priv)
struct fe_priv *priv = (struct fe_priv *)_priv;
struct mt7620_gsw *gsw = (struct mt7620_gsw *)priv->soc->swpriv;
u32 status;
int i, max = (gsw->port4 == PORT4_EPHY) ? (4) : (3);
int i, max = (gsw->port4_ephy) ? (4) : (3);
status = mtk_switch_r32(gsw, GSW_REG_ISR);
if (status & PORT_IRQ_ST_CHG)
@ -202,8 +202,8 @@ static void mt7620_hw_init(struct mt7620_gsw *gsw, int mdio_mode)
mtk_switch_w32(gsw, 0x7f7f7fe0, 0x0010);
/* setup port 4 */
if (gsw->port4 == PORT4_EPHY) {
u32 val = rt_sysc_r32(SYSC_REG_CFG1);
if (gsw->port4_ephy) {
val = rt_sysc_r32(SYSC_REG_CFG1);
val |= 3 << 14;
rt_sysc_w32(val, SYSC_REG_CFG1);
@ -255,7 +255,6 @@ int mtk_gsw_init(struct fe_priv *priv)
static int mt7620_gsw_probe(struct platform_device *pdev)
{
struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
const char *port4 = NULL;
struct mt7620_gsw *gsw;
struct device_node *np = pdev->dev.of_node;
u16 val;
@ -270,13 +269,7 @@ static int mt7620_gsw_probe(struct platform_device *pdev)
gsw->dev = &pdev->dev;
of_property_read_string(np, "mediatek,port4", &port4);
if (port4 && !strcmp(port4, "ephy"))
gsw->port4 = PORT4_EPHY;
else if (port4 && !strcmp(port4, "gmac"))
gsw->port4 = PORT4_EXT;
else
gsw->port4 = PORT4_EPHY;
gsw->port4_ephy = !of_property_read_bool(np, "mediatek,port4-gmac");
if (of_property_read_u16(np, "mediatek,ephy-base-address", &val) == 0)
gsw->ephy_base = val;

View File

@ -88,16 +88,11 @@ enum {
GSW_ATTR_PORT_UNTAG,
};
enum {
PORT4_EPHY = 0,
PORT4_EXT,
};
struct mt7620_gsw {
struct device *dev;
void __iomem *base;
int irq;
int port4;
bool port4_ephy;
unsigned long int autopoll;
u16 ephy_base;
};

View File

@ -141,7 +141,7 @@ static void mt7620_port_init(struct fe_priv *priv, struct device_node *np)
u32 val, mask = 0;
u32 val_delay = 0;
u32 mask_delay = GSW_REG_GPCx_TXDELAY | GSW_REG_GPCx_RXDELAY;
int min = (gsw->port4 == PORT4_EPHY) ? (5) : (4);
int min = (gsw->port4_ephy) ? (5) : (4);
if (!_id || (be32_to_cpu(*_id) < min) || (be32_to_cpu(*_id) > 5)) {
if (_id)