ramips: mt7620: add EPHY base mdio address changing possibility
In some boards is requred to change the ephy mdio base address. This patch add of property "mediatek,ephy-base-address" in gsw part, which allows to change ephy base address. Signed-off-by: Pawel Dembicki <paweldembicki@gmail.com> [fixed indentation in header file] Signed-off-by: Petr Štetiar <ynezz@true.cz>
This commit is contained in:
Pawel Dembicki
Petr Štetiar
parent
c02a9a2514
commit
391df37829
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@ -116,73 +116,82 @@ static void mt7620_hw_init(struct mt7620_gsw *gsw, int mdio_mode)
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mt7530_mdio_w32(gsw, 0x7a78, 0x855);
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} else {
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if (gsw->ephy_base) {
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/* set phy base addr to ephy_base */
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mtk_switch_w32(gsw, mtk_switch_r32(gsw, GSW_REG_GPC1) |
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(gsw->ephy_base << 16),
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GSW_REG_GPC1);
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fe_reset(BIT(24)); /* Resets the Ethernet PHY block. */
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}
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/* global page 4 */
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_mt7620_mii_write(gsw, 1, 31, 0x4000);
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_mt7620_mii_write(gsw, gsw->ephy_base + 1, 31, 0x4000);
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_mt7620_mii_write(gsw, 1, 17, 0x7444);
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_mt7620_mii_write(gsw, gsw->ephy_base + 1, 17, 0x7444);
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if (is_BGA)
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_mt7620_mii_write(gsw, 1, 19, 0x0114);
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_mt7620_mii_write(gsw, gsw->ephy_base + 1, 19, 0x0114);
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else
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_mt7620_mii_write(gsw, 1, 19, 0x0117);
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_mt7620_mii_write(gsw, gsw->ephy_base + 1, 19, 0x0117);
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_mt7620_mii_write(gsw, 1, 22, 0x10cf);
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_mt7620_mii_write(gsw, 1, 25, 0x6212);
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_mt7620_mii_write(gsw, 1, 26, 0x0777);
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_mt7620_mii_write(gsw, 1, 29, 0x4000);
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_mt7620_mii_write(gsw, 1, 28, 0xc077);
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_mt7620_mii_write(gsw, 1, 24, 0x0000);
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_mt7620_mii_write(gsw, gsw->ephy_base + 1, 22, 0x10cf);
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_mt7620_mii_write(gsw, gsw->ephy_base + 1, 25, 0x6212);
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_mt7620_mii_write(gsw, gsw->ephy_base + 1, 26, 0x0777);
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_mt7620_mii_write(gsw, gsw->ephy_base + 1, 29, 0x4000);
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_mt7620_mii_write(gsw, gsw->ephy_base + 1, 28, 0xc077);
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_mt7620_mii_write(gsw, gsw->ephy_base + 1, 24, 0x0000);
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/* global page 3 */
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_mt7620_mii_write(gsw, 1, 31, 0x3000);
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_mt7620_mii_write(gsw, 1, 17, 0x4838);
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_mt7620_mii_write(gsw, gsw->ephy_base + 1, 31, 0x3000);
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_mt7620_mii_write(gsw, gsw->ephy_base + 1, 17, 0x4838);
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/* global page 2 */
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_mt7620_mii_write(gsw, 1, 31, 0x2000);
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_mt7620_mii_write(gsw, gsw->ephy_base + 1, 31, 0x2000);
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if (is_BGA) {
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_mt7620_mii_write(gsw, 1, 21, 0x0515);
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_mt7620_mii_write(gsw, 1, 22, 0x0053);
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_mt7620_mii_write(gsw, 1, 23, 0x00bf);
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_mt7620_mii_write(gsw, 1, 24, 0x0aaf);
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_mt7620_mii_write(gsw, 1, 25, 0x0fad);
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_mt7620_mii_write(gsw, 1, 26, 0x0fc1);
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_mt7620_mii_write(gsw, gsw->ephy_base + 1, 21, 0x0515);
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_mt7620_mii_write(gsw, gsw->ephy_base + 1, 22, 0x0053);
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_mt7620_mii_write(gsw, gsw->ephy_base + 1, 23, 0x00bf);
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_mt7620_mii_write(gsw, gsw->ephy_base + 1, 24, 0x0aaf);
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_mt7620_mii_write(gsw, gsw->ephy_base + 1, 25, 0x0fad);
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_mt7620_mii_write(gsw, gsw->ephy_base + 1, 26, 0x0fc1);
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} else {
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_mt7620_mii_write(gsw, 1, 21, 0x0517);
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_mt7620_mii_write(gsw, 1, 22, 0x0fd2);
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_mt7620_mii_write(gsw, 1, 23, 0x00bf);
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_mt7620_mii_write(gsw, 1, 24, 0x0aab);
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_mt7620_mii_write(gsw, 1, 25, 0x00ae);
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_mt7620_mii_write(gsw, 1, 26, 0x0fff);
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_mt7620_mii_write(gsw, gsw->ephy_base + 1, 21, 0x0517);
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_mt7620_mii_write(gsw, gsw->ephy_base + 1, 22, 0x0fd2);
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_mt7620_mii_write(gsw, gsw->ephy_base + 1, 23, 0x00bf);
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_mt7620_mii_write(gsw, gsw->ephy_base + 1, 24, 0x0aab);
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_mt7620_mii_write(gsw, gsw->ephy_base + 1, 25, 0x00ae);
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_mt7620_mii_write(gsw, gsw->ephy_base + 1, 26, 0x0fff);
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}
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/* global page 1 */
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_mt7620_mii_write(gsw, 1, 31, 0x1000);
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_mt7620_mii_write(gsw, 1, 17, 0xe7f8);
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_mt7620_mii_write(gsw, gsw->ephy_base + 1, 31, 0x1000);
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_mt7620_mii_write(gsw, gsw->ephy_base + 1, 17, 0xe7f8);
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/* turn on all PHYs */
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for (i = 0; i <= 4; i++) {
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val = _mt7620_mii_read(gsw, i, 0);
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val = _mt7620_mii_read(gsw, gsw->ephy_base + i, 0);
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val &= ~BIT(11);
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_mt7620_mii_write(gsw, i, 0, val);
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_mt7620_mii_write(gsw, gsw->ephy_base + i, 0, val);
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}
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}
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/* global page 0 */
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_mt7620_mii_write(gsw, 1, 31, 0x8000);
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_mt7620_mii_write(gsw, 0, 30, 0xa000);
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_mt7620_mii_write(gsw, 1, 30, 0xa000);
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_mt7620_mii_write(gsw, 2, 30, 0xa000);
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_mt7620_mii_write(gsw, 3, 30, 0xa000);
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_mt7620_mii_write(gsw, gsw->ephy_base + 1, 31, 0x8000);
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_mt7620_mii_write(gsw, gsw->ephy_base + 0, 30, 0xa000);
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_mt7620_mii_write(gsw, gsw->ephy_base + 1, 30, 0xa000);
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_mt7620_mii_write(gsw, gsw->ephy_base + 2, 30, 0xa000);
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_mt7620_mii_write(gsw, gsw->ephy_base + 3, 30, 0xa000);
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_mt7620_mii_write(gsw, 0, 4, 0x05e1);
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_mt7620_mii_write(gsw, 1, 4, 0x05e1);
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_mt7620_mii_write(gsw, 2, 4, 0x05e1);
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_mt7620_mii_write(gsw, 3, 4, 0x05e1);
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_mt7620_mii_write(gsw, gsw->ephy_base + 0, 4, 0x05e1);
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_mt7620_mii_write(gsw, gsw->ephy_base + 1, 4, 0x05e1);
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_mt7620_mii_write(gsw, gsw->ephy_base + 2, 4, 0x05e1);
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_mt7620_mii_write(gsw, gsw->ephy_base + 3, 4, 0x05e1);
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/* global page 2 */
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_mt7620_mii_write(gsw, 1, 31, 0xa000);
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_mt7620_mii_write(gsw, 0, 16, 0x1111);
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_mt7620_mii_write(gsw, 1, 16, 0x1010);
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_mt7620_mii_write(gsw, 2, 16, 0x1515);
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_mt7620_mii_write(gsw, 3, 16, 0x0f0f);
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_mt7620_mii_write(gsw, gsw->ephy_base + 1, 31, 0xa000);
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_mt7620_mii_write(gsw, gsw->ephy_base + 0, 16, 0x1111);
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_mt7620_mii_write(gsw, gsw->ephy_base + 1, 16, 0x1010);
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_mt7620_mii_write(gsw, gsw->ephy_base + 2, 16, 0x1515);
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_mt7620_mii_write(gsw, gsw->ephy_base + 3, 16, 0x0f0f);
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/* CPU Port6 Force Link 1G, FC ON */
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mtk_switch_w32(gsw, 0x5e33b, GSW_REG_PORT_PMCR(6));
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@ -196,9 +205,9 @@ static void mt7620_hw_init(struct mt7620_gsw *gsw, int mdio_mode)
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val |= 3 << 14;
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rt_sysc_w32(val, SYSC_REG_CFG1);
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_mt7620_mii_write(gsw, 4, 30, 0xa000);
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_mt7620_mii_write(gsw, 4, 4, 0x05e1);
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_mt7620_mii_write(gsw, 4, 16, 0x1313);
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_mt7620_mii_write(gsw, gsw->ephy_base + 4, 30, 0xa000);
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_mt7620_mii_write(gsw, gsw->ephy_base + 4, 4, 0x05e1);
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_mt7620_mii_write(gsw, gsw->ephy_base + 4, 16, 0x1313);
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pr_info("gsw: setting port4 to ephy mode\n");
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} else if (!mdio_mode) {
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u32 val = rt_sysc_r32(SYSC_REG_CFG1);
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@ -247,6 +256,7 @@ static int mt7620_gsw_probe(struct platform_device *pdev)
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const char *port4 = NULL;
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struct mt7620_gsw *gsw;
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struct device_node *np = pdev->dev.of_node;
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u16 val;
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gsw = devm_kzalloc(&pdev->dev, sizeof(struct mt7620_gsw), GFP_KERNEL);
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if (!gsw)
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@ -266,6 +276,11 @@ static int mt7620_gsw_probe(struct platform_device *pdev)
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else
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gsw->port4 = PORT4_EPHY;
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if (of_property_read_u16(np, "mediatek,ephy-base-address", &val) == 0)
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gsw->ephy_base = val;
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else
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gsw->ephy_base = 0;
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gsw->irq = platform_get_irq(pdev, 0);
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platform_set_drvdata(pdev, gsw);
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@ -103,6 +103,7 @@ struct mt7620_gsw {
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int irq;
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int port4;
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unsigned long int autopoll;
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u16 ephy_base;
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};
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void mtk_switch_w32(struct mt7620_gsw *gsw, u32 val, unsigned reg);
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