mirror of
https://git.openwrt.org/openwrt/openwrt.git
synced 2024-06-15 19:53:59 +02:00
953bfe2eb3
There are only 2 options in the driver for the function of mt7620 internal switch port 4: EPHY mode (RJ-45, internal PHY) GMAC mode (RGMII, external PHY) Let the DTS property be boolean instead of string where EPHY mode is the default. Fix how the properties are written for all DTS that use them, and add missing nodes where applicable, and remove useless nodes, and minor DTS formatting. Signed-off-by: Michael Pratt <mcpratt@pm.me>
190 lines
2.8 KiB
Plaintext
190 lines
2.8 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
|
|
|
|
#include "mt7620a.dtsi"
|
|
|
|
#include <dt-bindings/gpio/gpio.h>
|
|
#include <dt-bindings/input/input.h>
|
|
|
|
/ {
|
|
compatible = "dlink,dwr-118-a1", "ralink,mt7620a-soc";
|
|
model = "D-Link DWR-118 A1";
|
|
|
|
aliases {
|
|
led-boot = &led_internet;
|
|
led-failsafe = &led_internet;
|
|
led-upgrade = &led_internet;
|
|
};
|
|
|
|
keys {
|
|
compatible = "gpio-keys";
|
|
|
|
wps {
|
|
label = "wps";
|
|
gpios = <&gpio0 12 GPIO_ACTIVE_LOW>;
|
|
linux,code = <KEY_WPS_BUTTON>;
|
|
};
|
|
|
|
reset {
|
|
label = "reset";
|
|
gpios = <&gpio0 13 GPIO_ACTIVE_LOW>;
|
|
linux,code = <KEY_RESTART>;
|
|
};
|
|
};
|
|
|
|
leds {
|
|
compatible = "gpio-leds";
|
|
|
|
wan {
|
|
label = "green:wan";
|
|
gpios = <&gpio3 0 GPIO_ACTIVE_LOW>;
|
|
};
|
|
|
|
led_internet: internet {
|
|
label = "green:internet";
|
|
gpios = <&gpio2 0 GPIO_ACTIVE_LOW>;
|
|
};
|
|
|
|
lan {
|
|
label = "green:lan";
|
|
gpios = <&gpio2 1 GPIO_ACTIVE_LOW>;
|
|
};
|
|
|
|
wlan2g {
|
|
label = "green:wlan2g";
|
|
gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
|
|
};
|
|
|
|
usb {
|
|
label = "green:usb";
|
|
gpios = <&gpio0 11 GPIO_ACTIVE_LOW>;
|
|
trigger-sources = <&ohci_port1>, <&ehci_port1>;
|
|
linux,default-trigger = "usbport";
|
|
};
|
|
};
|
|
|
|
gpio_export {
|
|
compatible = "gpio-export";
|
|
#size-cells = <0>;
|
|
|
|
usb {
|
|
gpio-export,name = "usb";
|
|
gpio-export,output = <0>;
|
|
gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;
|
|
};
|
|
};
|
|
};
|
|
|
|
&gpio1 {
|
|
status = "okay";
|
|
};
|
|
|
|
&gpio2 {
|
|
status = "okay";
|
|
};
|
|
|
|
&gpio3 {
|
|
status = "okay";
|
|
};
|
|
|
|
&spi0 {
|
|
status = "okay";
|
|
|
|
flash@0 {
|
|
compatible = "jedec,spi-nor";
|
|
reg = <0>;
|
|
spi-max-frequency = <80000000>;
|
|
|
|
partitions {
|
|
compatible = "fixed-partitions";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
|
|
partition@0 {
|
|
label = "jboot";
|
|
reg = <0x0 0x10000>;
|
|
read-only;
|
|
};
|
|
|
|
partition@10000 {
|
|
compatible = "amit,jimage";
|
|
label = "firmware";
|
|
reg = <0x10000 0xfe0000>;
|
|
};
|
|
|
|
config: partition@ff0000 {
|
|
label = "config";
|
|
reg = <0xff0000 0x10000>;
|
|
read-only;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
&ehci {
|
|
status = "okay";
|
|
};
|
|
|
|
&ohci {
|
|
status = "okay";
|
|
};
|
|
|
|
&state_default {
|
|
default {
|
|
groups = "ephy", "uartf", "spi refclk", "wled";
|
|
function = "gpio";
|
|
};
|
|
};
|
|
|
|
&pcie {
|
|
status = "okay";
|
|
};
|
|
|
|
&pcie0 {
|
|
wifi@0,0 {
|
|
reg = <0x0000 0 0 0 0>;
|
|
mtd-mac-address = <&config 0xe496>;
|
|
mtd-mac-address-increment = <(2)>;
|
|
mediatek,mtd-eeprom = <&config 0xe083>;
|
|
|
|
led {
|
|
led-sources = <0>;
|
|
led-active-low;
|
|
};
|
|
};
|
|
};
|
|
|
|
ðernet {
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&rgmii1_pins &rgmii2_pins &mdio_pins>;
|
|
|
|
port@4 {
|
|
status = "okay";
|
|
phy-handle = <&phy4>;
|
|
phy-mode = "rgmii";
|
|
};
|
|
|
|
port@5 {
|
|
status = "okay";
|
|
phy-handle = <&phy5>;
|
|
phy-mode = "rgmii";
|
|
};
|
|
|
|
mdio-bus {
|
|
status = "okay";
|
|
|
|
phy4: ethernet-phy@4 {
|
|
reg = <4>;
|
|
phy-mode = "rgmii-rxid";
|
|
};
|
|
|
|
phy5: ethernet-phy@5 {
|
|
reg = <5>;
|
|
phy-mode = "rgmii-rxid";
|
|
};
|
|
};
|
|
};
|
|
|
|
&gsw {
|
|
mediatek,port4-gmac;
|
|
};
|