74 lines
2.0 KiB
Diff
74 lines
2.0 KiB
Diff
--- a/drivers/usb/host/Kconfig
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+++ b/drivers/usb/host/Kconfig
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@@ -339,6 +339,13 @@ config USB_OCTEON_EHCI
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USB 2.0 device support. All CN6XXX based chips with USB are
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supported.
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+config USB_EHCI_OXNAS
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+ tristate "OXNAS EHCI Module"
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+ depends on USB_EHCI_HCD && ARCH_OXNAS
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+ select USB_EHCI_ROOT_HUB_TT
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+ help
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+ Enable support for the OX820 SOC's on-chip EHCI controller.
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+
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endif # USB_EHCI_HCD
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config USB_OXU210HP_HCD
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--- a/drivers/usb/host/Makefile
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+++ b/drivers/usb/host/Makefile
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@@ -46,6 +46,7 @@ obj-$(CONFIG_USB_EHCI_HCD_STI) += ehci-s
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obj-$(CONFIG_USB_EHCI_EXYNOS) += ehci-exynos.o
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obj-$(CONFIG_USB_EHCI_HCD_AT91) += ehci-atmel.o
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obj-$(CONFIG_USB_EHCI_BRCMSTB) += ehci-brcm.o
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+obj-$(CONFIG_USB_EHCI_OXNAS) += ehci-oxnas.o
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obj-$(CONFIG_USB_OXU210HP_HCD) += oxu210hp-hcd.o
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obj-$(CONFIG_USB_ISP116X_HCD) += isp116x-hcd.o
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--- a/arch/arm/boot/dts/ox820.dtsi
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+++ b/arch/arm/boot/dts/ox820.dtsi
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@@ -106,6 +106,31 @@
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status = "disabled";
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};
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+ ehci: ehci@40200100 {
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+ compatible = "plxtech,nas782x-ehci";
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+ reg = <0x40200100 0xf00>;
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+ interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
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+ clocks = <&stdclk CLK_820_USBMPH>, <&pllb>, <&stdclk CLK_820_REF600>;
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+ clock-names = "usb", "refsrc", "phyref";
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+ resets = <&reset RESET_USBHS>, <&reset RESET_USBPHYA>, <&reset RESET_USBPHYB>;
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+ reset-names = "host", "phya", "phyb";
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+ oxsemi,sys-ctrl = <&sys>;
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+ /* Otherwise ref300 is used, which is derived from sata phy
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+ * in that case, usb depends on sata initialization */
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+ /* FIXME: how to make this dependency explicit ? */
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+ oxsemi,ehci_use_pllb;
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+ status = "disabled";
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+
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+ ehci_port1: port@1 {
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+ reg = <1>;
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+ #trigger-source-cells = <0>;
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+ };
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+ ehci_port2: port@2 {
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+ reg = <2>;
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+ #trigger-source-cells = <0>;
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+ };
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+ };
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+
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apb-bridge@44000000 {
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#address-cells = <1>;
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#size-cells = <1>;
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--- a/arch/arm/boot/dts/ox820-cloudengines-pogoplug-series-3.dts
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+++ b/arch/arm/boot/dts/ox820-cloudengines-pogoplug-series-3.dts
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@@ -105,6 +105,10 @@
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};
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};
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+&ehci {
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+ status = "okay";
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+};
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+
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ða {
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status = "okay";
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