--- a/drivers/usb/host/Kconfig +++ b/drivers/usb/host/Kconfig @@ -339,6 +339,13 @@ config USB_OCTEON_EHCI USB 2.0 device support. All CN6XXX based chips with USB are supported. +config USB_EHCI_OXNAS + tristate "OXNAS EHCI Module" + depends on USB_EHCI_HCD && ARCH_OXNAS + select USB_EHCI_ROOT_HUB_TT + help + Enable support for the OX820 SOC's on-chip EHCI controller. + endif # USB_EHCI_HCD config USB_OXU210HP_HCD --- a/drivers/usb/host/Makefile +++ b/drivers/usb/host/Makefile @@ -46,6 +46,7 @@ obj-$(CONFIG_USB_EHCI_HCD_STI) += ehci-s obj-$(CONFIG_USB_EHCI_EXYNOS) += ehci-exynos.o obj-$(CONFIG_USB_EHCI_HCD_AT91) += ehci-atmel.o obj-$(CONFIG_USB_EHCI_BRCMSTB) += ehci-brcm.o +obj-$(CONFIG_USB_EHCI_OXNAS) += ehci-oxnas.o obj-$(CONFIG_USB_OXU210HP_HCD) += oxu210hp-hcd.o obj-$(CONFIG_USB_ISP116X_HCD) += isp116x-hcd.o --- a/arch/arm/boot/dts/ox820.dtsi +++ b/arch/arm/boot/dts/ox820.dtsi @@ -106,6 +106,31 @@ status = "disabled"; }; + ehci: ehci@40200100 { + compatible = "plxtech,nas782x-ehci"; + reg = <0x40200100 0xf00>; + interrupts = ; + clocks = <&stdclk CLK_820_USBMPH>, <&pllb>, <&stdclk CLK_820_REF600>; + clock-names = "usb", "refsrc", "phyref"; + resets = <&reset RESET_USBHS>, <&reset RESET_USBPHYA>, <&reset RESET_USBPHYB>; + reset-names = "host", "phya", "phyb"; + oxsemi,sys-ctrl = <&sys>; + /* Otherwise ref300 is used, which is derived from sata phy + * in that case, usb depends on sata initialization */ + /* FIXME: how to make this dependency explicit ? */ + oxsemi,ehci_use_pllb; + status = "disabled"; + + ehci_port1: port@1 { + reg = <1>; + #trigger-source-cells = <0>; + }; + ehci_port2: port@2 { + reg = <2>; + #trigger-source-cells = <0>; + }; + }; + apb-bridge@44000000 { #address-cells = <1>; #size-cells = <1>; --- a/arch/arm/boot/dts/ox820-cloudengines-pogoplug-series-3.dts +++ b/arch/arm/boot/dts/ox820-cloudengines-pogoplug-series-3.dts @@ -105,6 +105,10 @@ }; }; +&ehci { + status = "okay"; +}; + ða { status = "okay";