589 lines
10 KiB
Plaintext
589 lines
10 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
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/* Copyright (c) 2021, Robert Marko <robimarko@gmail.com> */
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/dts-v1/;
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#include "ipq8074.dtsi"
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#include "ipq8074-hk-cpu.dtsi"
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#include "ipq8074-ess.dtsi"
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/input/input.h>
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#include <dt-bindings/leds/common.h>
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/ {
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model = "Xiaomi AX9000";
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compatible = "xiaomi,ax9000", "qcom,ipq8074";
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aliases {
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serial0 = &blsp1_uart5;
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led-boot = &led_system_yellow;
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led-failsafe = &led_system_yellow;
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led-running = &led_system_blue;
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led-upgrade = &led_system_yellow;
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label-mac-device = &dp5;
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};
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chosen {
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stdout-path = "serial0:115200n8";
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bootargs-append = " root=/dev/ubiblock0_0";
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};
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keys {
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compatible = "gpio-keys";
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reset {
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label = "reset";
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gpios = <&tlmm 47 GPIO_ACTIVE_LOW>;
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linux,code = <KEY_RESTART>;
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};
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wps {
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label = "wps"; /* Labeled Mesh on the device */
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gpios = <&tlmm 46 GPIO_ACTIVE_LOW>;
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linux,code = <KEY_WPS_BUTTON>;
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};
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};
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leds {
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compatible = "gpio-leds";
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led_system_blue: system-blue {
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gpios = <&tlmm 48 GPIO_ACTIVE_HIGH>;
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color = <LED_COLOR_ID_BLUE>;
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};
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led_system_yellow: system-yellow {
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gpios = <&tlmm 52 GPIO_ACTIVE_HIGH>;
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color = <LED_COLOR_ID_YELLOW>;
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};
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network-yellow {
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gpios = <&tlmm 50 GPIO_ACTIVE_HIGH>;
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color = <LED_COLOR_ID_YELLOW>;
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};
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network-blue {
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gpios = <&tlmm 51 GPIO_ACTIVE_HIGH>;
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color = <LED_COLOR_ID_BLUE>;
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};
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top-red {
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gpios = <&tlmm 63 GPIO_ACTIVE_HIGH>;
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color = <LED_COLOR_ID_RED>;
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default-state = "keep";
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};
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top-green {
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gpios = <&tlmm 64 GPIO_ACTIVE_HIGH>;
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color = <LED_COLOR_ID_GREEN>;
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default-state = "keep";
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};
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top-blue {
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gpios = <&tlmm 66 GPIO_ACTIVE_HIGH>;
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color = <LED_COLOR_ID_BLUE>;
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default-state = "keep";
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};
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};
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};
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&tlmm {
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mdio_pins: mdio-pins {
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mdc {
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pins = "gpio68";
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function = "mdc";
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drive-strength = <8>;
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bias-pull-up;
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};
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mdio {
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pins = "gpio69";
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function = "mdio";
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drive-strength = <8>;
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bias-pull-up;
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};
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};
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i2c_pins: i2c-pins {
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pins = "gpio0", "gpio2";
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function = "blsp5_i2c";
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drive-strength = <8>;
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bias-disable;
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};
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};
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&blsp1_uart5 {
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status = "okay";
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};
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&blsp1_i2c6 {
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status = "okay";
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pinctrl-0 = <&i2c_pins>;
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pinctrl-names = "default";
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};
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&prng {
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status = "okay";
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};
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&cryptobam {
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status = "okay";
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};
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&crypto {
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status = "okay";
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};
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&qpic_bam {
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status = "okay";
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};
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&qpic_nand {
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status = "okay";
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/*
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* Bootloader will find the NAND DT node by the compatible and
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* then "fixup" it by adding the partitions from the SMEM table
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* using the legacy bindings thus making it impossible for us
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* to change the partition table or utilize NVMEM for calibration.
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* So add a dummy partitions node that bootloader will populate
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* and set it as disabled so the kernel ignores it instead of
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* printing warnings due to the broken way bootloader adds the
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* partitions.
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*/
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partitions {
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status = "disabled";
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};
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nand@0 {
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reg = <0>;
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nand-ecc-strength = <4>;
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nand-ecc-step-size = <512>;
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nand-bus-width = <8>;
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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partition@0 {
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label = "0:sbl1";
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reg = <0x0 0x100000>;
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read-only;
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};
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partition@100000 {
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label = "0:mibib";
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reg = <0x100000 0x100000>;
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read-only;
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};
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partition@200000 {
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label = "0:bootconfig";
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reg = <0x200000 0x80000>;
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read-only;
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};
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partition@280000 {
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label = "0:bootconfig1";
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reg = <0x280000 0x80000>;
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read-only;
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};
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partition@300000 {
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label = "0:qsee";
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reg = <0x300000 0x300000>;
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read-only;
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};
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partition@600000 {
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label = "0:qsee_1";
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reg = <0x600000 0x300000>;
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read-only;
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};
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partition@900000 {
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label = "0:devcfg";
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reg = <0x900000 0x80000>;
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read-only;
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};
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partition@980000 {
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label = "0:devcfg_1";
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reg = <0x980000 0x80000>;
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read-only;
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};
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partition@a00000 {
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label = "0:apdp";
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reg = <0xa00000 0x80000>;
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read-only;
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};
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partition@a80000 {
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label = "0:apdp_1";
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reg = <0xa80000 0x80000>;
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read-only;
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};
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partition@b00000 {
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label = "0:rpm";
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reg = <0xb00000 0x80000>;
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read-only;
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};
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partition@b80000 {
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label = "0:rpm_1";
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reg = <0xb80000 0x80000>;
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read-only;
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};
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partition@c00000 {
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label = "0:cdt";
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reg = <0xc00000 0x80000>;
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read-only;
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};
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partition@c80000 {
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label = "0:cdt_1";
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reg = <0xc80000 0x80000>;
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read-only;
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};
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partition@d00000 {
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label = "0:appsblenv";
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reg = <0xd00000 0x80000>;
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};
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partition@d80000 {
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label = "0:appsbl";
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reg = <0xd80000 0x100000>;
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read-only;
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};
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partition@e80000 {
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label = "0:appsbl_1";
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reg = <0xe80000 0x100000>;
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read-only;
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};
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partition@f80000 {
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label = "0:art";
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reg = <0xf80000 0x80000>;
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read-only;
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nvmem-layout {
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compatible = "fixed-layout";
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#address-cells = <1>;
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#size-cells = <1>;
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macaddr_dp1: macaddr@0 {
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reg = <0x0 0x6>;
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};
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macaddr_dp2: macaddr@6 {
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reg = <0x6 0x6>;
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};
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macaddr_dp3: macaddr@c {
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reg = <0xc 0x6>;
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};
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macaddr_dp4: macaddr@12 {
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reg = <0x12 0x6>;
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};
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macaddr_dp5: macaddr@18 {
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reg = <0x18 0x6>;
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};
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caldata_qca9889: caldata@4d000 {
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reg = <0x4d000 0x844>;
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};
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};
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};
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partition@1000000 {
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label = "bdata";
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reg = <0x1000000 0x80000>;
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};
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partition@1080000 {
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/* This is crash + crash_syslog parts combined */
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label = "pstore";
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reg = <0x1080000 0x100000>;
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};
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partition@1180000 {
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label = "ubi_kernel";
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reg = <0x1180000 0x3800000>;
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};
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partition@4980000 {
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label = "rootfs";
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reg = <0x4980000 0xb680000>;
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};
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};
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};
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};
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&qusb_phy_0 {
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status = "okay";
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};
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&ssphy_0 {
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status = "okay";
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};
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&usb_0 {
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status = "okay";
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};
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&mdio {
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status = "okay";
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pinctrl-0 = <&mdio_pins>;
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pinctrl-names = "default";
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reset-gpios = <&tlmm 37 GPIO_ACTIVE_LOW>;
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ethernet-phy-package@0 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "qcom,qca8075-package";
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reg = <0>;
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qcom,package-mode = "qsgmii";
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qca8075_0: ethernet-phy@0 {
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compatible = "ethernet-phy-ieee802.3-c22";
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reg = <0>;
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leds {
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#address-cells = <1>;
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#size-cells = <0>;
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led@0 {
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reg = <0>;
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color = <LED_COLOR_ID_GREEN>;
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function = LED_FUNCTION_LAN;
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default-state = "keep";
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};
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};
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};
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qca8075_1: ethernet-phy@1 {
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compatible = "ethernet-phy-ieee802.3-c22";
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reg = <1>;
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leds {
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#address-cells = <1>;
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#size-cells = <0>;
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led@0 {
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reg = <0>;
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color = <LED_COLOR_ID_GREEN>;
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function = LED_FUNCTION_LAN;
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default-state = "keep";
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};
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};
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};
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qca8075_2: ethernet-phy@2 {
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compatible = "ethernet-phy-ieee802.3-c22";
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reg = <2>;
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leds {
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#address-cells = <1>;
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#size-cells = <0>;
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led@0 {
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reg = <0>;
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color = <LED_COLOR_ID_GREEN>;
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function = LED_FUNCTION_LAN;
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default-state = "keep";
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};
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};
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};
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qca8075_3: ethernet-phy@3 {
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compatible = "ethernet-phy-ieee802.3-c22";
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reg = <3>;
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leds {
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#address-cells = <1>;
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#size-cells = <0>;
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led@0 {
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reg = <0>;
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color = <LED_COLOR_ID_GREEN>;
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function = LED_FUNCTION_LAN;
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default-state = "keep";
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};
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};
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};
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};
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qca8081: ethernet-phy@24 {
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compatible = "ethernet-phy-id004d.d101";
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reg = <24>;
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reset-deassert-us = <10000>;
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reset-gpios = <&tlmm 44 GPIO_ACTIVE_LOW>;
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leds {
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#address-cells = <1>;
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#size-cells = <0>;
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led@0 {
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reg = <0>;
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color = <LED_COLOR_ID_GREEN>;
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function = LED_FUNCTION_WAN;
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default-state = "keep";
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};
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};
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};
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};
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&switch {
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status = "okay";
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switch_lan_bmp = <(ESS_PORT1 | ESS_PORT2 | ESS_PORT3 | ESS_PORT4)>; /* lan port bitmap */
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switch_wan_bmp = <ESS_PORT5>; /* wan port bitmap */
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switch_mac_mode = <MAC_MODE_QSGMII>; /* mac mode for uniphy instance0*/
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switch_mac_mode1 = <MAC_MODE_SGMII_PLUS>; /* mac mode for uniphy instance1*/
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qcom,port_phyinfo {
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port@1 {
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port_id = <1>;
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phy_address = <0>;
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};
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port@2 {
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port_id = <2>;
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phy_address = <1>;
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};
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port@3 {
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port_id = <3>;
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phy_address = <2>;
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};
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port@4 {
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port_id = <4>;
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phy_address = <3>;
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};
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port@5 {
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port_id = <5>;
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phy_address = <24>;
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port_mac_sel = "QGMAC_PORT";
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};
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};
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};
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&edma {
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status = "okay";
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};
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&dp1 {
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status = "okay";
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phy-mode = "qsgmii";
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phy-handle = <&qca8075_0>;
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label = "lan4";
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nvmem-cells = <&macaddr_dp1>;
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nvmem-cell-names = "mac-address";
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};
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&dp2 {
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status = "okay";
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phy-mode = "qsgmii";
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phy-handle = <&qca8075_1>;
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label = "lan3";
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nvmem-cells = <&macaddr_dp2>;
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nvmem-cell-names = "mac-address";
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};
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&dp3 {
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status = "okay";
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phy-mode = "qsgmii";
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phy-handle = <&qca8075_2>;
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label = "lan2";
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nvmem-cells = <&macaddr_dp3>;
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nvmem-cell-names = "mac-address";
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};
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&dp4 {
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status = "okay";
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phy-mode = "qsgmii";
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phy-handle = <&qca8075_3>;
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label = "lan1";
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nvmem-cells = <&macaddr_dp4>;
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nvmem-cell-names = "mac-address";
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};
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&dp5 {
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status = "okay";
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phy-mode = "sgmii";
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phy-handle = <&qca8081>;
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label = "wan";
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nvmem-cells = <&macaddr_dp5>;
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nvmem-cell-names = "mac-address";
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};
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&pcie_qmp0 {
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status = "okay";
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};
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&pcie0 {
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status = "okay";
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perst-gpio = <&tlmm 58 GPIO_ACTIVE_LOW>;
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bridge@0,0 {
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reg = <0x00000000 0 0 0 0>;
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#address-cells = <3>;
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#size-cells = <2>;
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ranges;
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wifi@1,0 {
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status = "okay";
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/* ath11k has no DT compatible for PCI cards */
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compatible = "pci17cb,1104";
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reg = <0x00010000 0 0 0 0>;
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qcom,ath11k-calibration-variant = "Xiaomi-AX9000";
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};
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};
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};
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&pcie_qmp1 {
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status = "okay";
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};
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&pcie1 {
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status = "okay";
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perst-gpio = <&tlmm 62 GPIO_ACTIVE_HIGH>;
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bridge@1,0 {
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reg = <0x00010000 0 0 0 0>;
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#address-cells = <3>;
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#size-cells = <2>;
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ranges;
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wifi@1,0 {
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status = "okay";
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compatible = "qcom,ath10k";
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reg = <0x00010000 0 0 0 0>;
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qcom,ath10k-calibration-variant = "Xiaomi-AX9000";
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nvmem-cell-names = "calibration";
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nvmem-cells = <&caldata_qca9889>;
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};
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};
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};
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&wifi {
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status = "okay";
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qcom,ath11k-calibration-variant = "Xiaomi-AX9000";
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};
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