arm-trusted-firmware-mvebu: update to v2.5
Revert to using the checked in `tbb_linux` image tool binary since building it drags in the rather big Crypto++ project. Cherry-pick the post-release UART fixes. Switch to AUTORELEASE while at it. Signed-off-by: Andre Heider <a.heider@gmail.com>
This commit is contained in:
Andre Heider
Hauke Mehrtens
parent
0c111ce237
commit
b40705b677
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@ -7,9 +7,9 @@
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include $(TOPDIR)/rules.mk
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PKG_VERSION:=2.4
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PKG_RELEASE:=1
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PKG_HASH:=bf3eb3617a74cddd7fb0e0eacbfe38c3258ee07d4c8ed730deef7a175cc3d55b
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PKG_VERSION:=2.5
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PKG_RELEASE:=$(AUTORELEASE)
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PKG_HASH:=ad8a2ffcbcd12d919723da07630fc0840c3c2fba7656d1462e45488e42995d7c
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PKG_MAINTAINER:=Vladimir Vid <vladimir.vid@sartura.hr>
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@ -111,12 +111,15 @@ TFA_MAKE_FLAGS += \
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BL33=$(STAGING_DIR_IMAGE)/$(UBOOT)-u-boot.bin \
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MV_DDR_PATH=$(STAGING_DIR_IMAGE)/$(MV_DDR_NAME) \
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WTP=$(STAGING_DIR_IMAGE)/$(A3700_UTILS_NAME) \
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USE_COHERENT_MEM=0 \
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FIP_ALIGN=0x100 \
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DDR_TOPOLOGY=$(DDR_TOPOLOGY) \
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CLOCKSPRESET=$(CLOCKSPRESET) \
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A3700_UTILS_COMMIT_ID=$(A3700_UTILS_RELEASE) \
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MV_DDR_COMMIT_ID=$(MV_DDR_RELEASE) \
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all \
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mrvl_flash
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mrvl_flash \
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mrvl_uart
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A3700_UTILS_NAME:=a3700-utils
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A3700_UTILS_RELEASE:=5598e150
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@ -172,8 +175,10 @@ define Build/Prepare
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mkdir -p $(STAGING_DIR_IMAGE)
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$(TAR) -C $(STAGING_DIR_IMAGE) -xf $(DL_DIR)/$(A3700_UTILS_SOURCE)
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echo "master" > $(STAGING_DIR_IMAGE)/$(A3700_UTILS_NAME)/branch.txt
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$(call PatchDir/Default,$(STAGING_DIR_IMAGE)/$(A3700_UTILS_NAME),./patches-a3700-utils)
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$(TAR) -C $(STAGING_DIR_IMAGE) -xf $(DL_DIR)/$(MV_DDR_SOURCE)
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echo "master" > $(STAGING_DIR_IMAGE)/$(MV_DDR_NAME)/branch.txt
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$(call PatchDir/Default,$(STAGING_DIR_IMAGE)/$(MV_DDR_NAME),./patches-mv-ddr-marvell)
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$(TAR) -C $(STAGING_DIR_IMAGE) -xf $(DL_DIR)/$(LINARO_SOURCE)
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endef
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@ -0,0 +1,20 @@
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--- a/plat/marvell/armada/a3k/common/a3700_common.mk
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+++ b/plat/marvell/armada/a3k/common/a3700_common.mk
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@@ -76,7 +76,7 @@ $(if $(wildcard $(value WTP)/*),,$(error
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$(if $(shell test -s "$(value WTP)/branch.txt" || git -C $(value WTP) rev-parse --show-cdup 2>&1),$(error "'WTP=$(value WTP)' was specified, but '$(value WTP)' does not contain valid Marvell a3700_utils release tarball nor git repository"))
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DOIMAGEPATH := $(WTP)
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-DOIMAGETOOL := $(DOIMAGEPATH)/wtptp/src/TBB_Linux/release/TBB_linux
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+DOIMAGETOOL := $(DOIMAGEPATH)/wtptp/linux/tbb_linux
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BUILD_UART := uart-images
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UART_IMAGE := $(BUILD_UART).tgz.bin
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@@ -132,7 +132,7 @@ TIMBLDUARTARGS := $(MARVELL_SECURE_BOOT
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CRYPTOPP_LIBDIR ?= $(CRYPTOPP_PATH)
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CRYPTOPP_INCDIR ?= $(CRYPTOPP_PATH)
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-$(DOIMAGETOOL): FORCE
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+$(DOIMAGETOOL):
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$(if $(CRYPTOPP_LIBDIR),,$(error "Platform '$(PLAT)' for WTP image tool requires CRYPTOPP_PATH or CRYPTOPP_LIBDIR. Please set CRYPTOPP_PATH or CRYPTOPP_LIBDIR to point to the right directory"))
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$(if $(CRYPTOPP_INCDIR),,$(error "Platform '$(PLAT)' for WTP image tool requires CRYPTOPP_PATH or CRYPTOPP_INCDIR. Please set CRYPTOPP_PATH or CRYPTOPP_INCDIR to point to the right directory"))
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$(if $(wildcard $(CRYPTOPP_LIBDIR)/*),,$(error "Either 'CRYPTOPP_PATH' or 'CRYPTOPP_LIB' was set to '$(CRYPTOPP_LIBDIR)', but '$(CRYPTOPP_LIBDIR)' does not exist"))
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@ -0,0 +1,60 @@
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From 66a7752834382595d26214783ae4698fd1f00bd6 Mon Sep 17 00:00:00 2001
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From: =?UTF-8?q?Pali=20Roh=C3=A1r?= <pali@kernel.org>
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Date: Thu, 13 May 2021 14:53:44 +0200
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Subject: [PATCH] fix(plat/marvell/a3720/uart): fix UART clock rate value and
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divisor calculation
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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UART parent clock is by default the platform's xtal clock, which is
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25 MHz.
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The value defined in the driver, though, is 25.8048 MHz. This is a hack
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for the suboptimal divisor calculation
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Divisor = UART clock / (16 * baudrate)
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which does not use rounding division, resulting in a suboptimal value
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for divisor if the correct parent clock rate was used.
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Change the code for divisor calculation to
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Divisor = Round(UART clock / (16 * baudrate))
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and change the parent clock rate value to 25 MHz.
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The final UART divisor for default baudrate 115200 is not affected by
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this change.
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(Note that the parent clock rate should not be defined via a macro,
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since the xtal clock can also be 40 MHz. This is outside of the scope of
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this fix, though.)
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Signed-off-by: Pali Rohár <pali@kernel.org>
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Change-Id: Iaa401173df87aec94f2dd1b38a90fb6ed0bf0ec6
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---
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drivers/marvell/uart/a3700_console.S | 3 ++-
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plat/marvell/armada/a3k/common/include/platform_def.h | 2 +-
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2 files changed, 3 insertions(+), 2 deletions(-)
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--- a/drivers/marvell/uart/a3700_console.S
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+++ b/drivers/marvell/uart/a3700_console.S
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@@ -45,8 +45,9 @@ func console_a3700_core_init
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cbz w2, init_fail
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/* Program the baudrate */
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- /* Divisor = Uart clock / (16 * baudrate) */
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+ /* Divisor = Round(Uartclock / (16 * baudrate)) */
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lsl w2, w2, #4
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+ add w1, w1, w2, lsr #1
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udiv w2, w1, w2
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and w2, w2, #0x3ff
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--- a/plat/marvell/armada/a3k/common/include/platform_def.h
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+++ b/plat/marvell/armada/a3k/common/include/platform_def.h
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@@ -164,7 +164,7 @@
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* PL011 related constants
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*/
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#define PLAT_MARVELL_BOOT_UART_BASE (MVEBU_REGS_BASE + 0x12000)
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-#define PLAT_MARVELL_BOOT_UART_CLK_IN_HZ 25804800
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+#define PLAT_MARVELL_BOOT_UART_CLK_IN_HZ 25000000
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#define PLAT_MARVELL_CRASH_UART_BASE PLAT_MARVELL_BOOT_UART_BASE
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#define PLAT_MARVELL_CRASH_UART_CLK_IN_HZ PLAT_MARVELL_BOOT_UART_CLK_IN_HZ
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@ -0,0 +1,53 @@
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From b9185c75f7ec2b600ebe0d49281e216a2456b764 Mon Sep 17 00:00:00 2001
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From: =?UTF-8?q?Pali=20Roh=C3=A1r?= <pali@kernel.org>
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Date: Thu, 13 May 2021 15:11:06 +0200
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Subject: [PATCH] fix(plat/marvell/a3720/uart): fix configuring UART clock
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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When configuring the UART_BAUD_REG register, the function
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console_a3700_core_init() currently only changes the baud divisor field,
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leaving other fields to their previous value.
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This is incorrect, because the baud divisor is computed with the
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assumption that the parent clock rate is 25 MHz, and since the other
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fields in this register configure the parent clock, which could have
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been changed by U-Boot or Linux.
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Fix this function to also configure the other fields so that the UART
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parent clock is selected to be the xtal clock.
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For example without this change TF-A prints only
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ERROR: a3700_system_off needs to be implemented
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followed by garbage after plat_crash_console_init() is called.
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After applying this change instead of garbage it also print crash info:
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PANIC at PC : 0x0000000004023800
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Signed-off-by: Pali Rohár <pali@kernel.org>
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Change-Id: I72f338355cc60d939b8bb978d9c7fdd576416b81
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---
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drivers/marvell/uart/a3700_console.S | 7 ++-----
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1 file changed, 2 insertions(+), 5 deletions(-)
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--- a/drivers/marvell/uart/a3700_console.S
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+++ b/drivers/marvell/uart/a3700_console.S
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@@ -49,12 +49,9 @@ func console_a3700_core_init
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lsl w2, w2, #4
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add w1, w1, w2, lsr #1
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udiv w2, w1, w2
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- and w2, w2, #0x3ff
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+ and w2, w2, #0x3ff /* clear all other bits to use default clock */
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- ldr w3, [x0, #UART_BAUD_REG]
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- bic w3, w3, 0x3ff
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- orr w3, w3, w2
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- str w3, [x0, #UART_BAUD_REG]/* set baud rate divisor */
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+ str w2, [x0, #UART_BAUD_REG]/* set baud rate divisor */
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/* Set UART to default 16X scheme */
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mov w3, #0
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@ -0,0 +1,122 @@
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From 3133625859b74df42deddd80b705578af6fc2fea Mon Sep 17 00:00:00 2001
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From: =?UTF-8?q?Pali=20Roh=C3=A1r?= <pali@kernel.org>
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Date: Fri, 14 May 2021 13:21:56 +0200
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Subject: [PATCH] refactor(plat/marvell/uart): de-duplicate PLAT_MARVELL_UART
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macros
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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Macros PLAT_MARVELL_BOOT_UART* and PLAT_MARVELL_CRASH_UART* are defined
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to same values. De-duplicate them into PLAT_MARVELL_UART* macros.
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Signed-off-by: Pali Rohár <pali@kernel.org>
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Change-Id: Iae5daf7cad6a971e6f3dbe561df3d0174106ca7f
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---
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plat/marvell/armada/a3k/common/include/platform_def.h | 7 ++-----
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plat/marvell/armada/a8k/a80x0_puzzle/board/system_power.c | 4 ++--
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plat/marvell/armada/a8k/common/include/platform_def.h | 7 ++-----
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plat/marvell/armada/common/aarch64/marvell_helpers.S | 8 ++++----
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plat/marvell/armada/common/marvell_console.c | 8 ++++----
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5 files changed, 14 insertions(+), 20 deletions(-)
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--- a/plat/marvell/armada/a3k/common/include/platform_def.h
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+++ b/plat/marvell/armada/a3k/common/include/platform_def.h
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@@ -163,11 +163,8 @@
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/*
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* PL011 related constants
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*/
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-#define PLAT_MARVELL_BOOT_UART_BASE (MVEBU_REGS_BASE + 0x12000)
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-#define PLAT_MARVELL_BOOT_UART_CLK_IN_HZ 25000000
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-
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-#define PLAT_MARVELL_CRASH_UART_BASE PLAT_MARVELL_BOOT_UART_BASE
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-#define PLAT_MARVELL_CRASH_UART_CLK_IN_HZ PLAT_MARVELL_BOOT_UART_CLK_IN_HZ
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+#define PLAT_MARVELL_UART_BASE (MVEBU_REGS_BASE + 0x12000)
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+#define PLAT_MARVELL_UART_CLK_IN_HZ 25000000
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#define PLAT_MARVELL_BL31_RUN_UART_BASE PLAT_MARVELL_BOOT_UART_BASE
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#define PLAT_MARVELL_BL31_RUN_UART_CLK_IN_HZ PLAT_MARVELL_BOOT_UART_CLK_IN_HZ
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--- a/plat/marvell/armada/a8k/a80x0_puzzle/board/system_power.c
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+++ b/plat/marvell/armada/a8k/a80x0_puzzle/board/system_power.c
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@@ -41,8 +41,8 @@ int system_power_off(void)
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len = sizeof(system_off_now);
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system_off_now[len - 1] = add_xor_checksum(system_off_now, len);
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- console_16550_register(PLAT_MARVELL_BOOT_UART_BASE + 0x100,
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- PLAT_MARVELL_BOOT_UART_CLK_IN_HZ, 115200, &console);
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+ console_16550_register(PLAT_MARVELL_UART_BASE + 0x100,
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+ PLAT_MARVELL_UART_CLK_IN_HZ, 115200, &console);
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/* Send system_off_now to console */
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for (i = 0; i < len; i++) {
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--- a/plat/marvell/armada/a8k/common/include/platform_def.h
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+++ b/plat/marvell/armada/a8k/common/include/platform_def.h
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@@ -168,11 +168,8 @@
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/*
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* PL011 related constants
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*/
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-#define PLAT_MARVELL_BOOT_UART_BASE (MVEBU_REGS_BASE + 0x512000)
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-#define PLAT_MARVELL_BOOT_UART_CLK_IN_HZ 200000000
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-
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-#define PLAT_MARVELL_CRASH_UART_BASE PLAT_MARVELL_BOOT_UART_BASE
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-#define PLAT_MARVELL_CRASH_UART_CLK_IN_HZ PLAT_MARVELL_BOOT_UART_CLK_IN_HZ
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+#define PLAT_MARVELL_UART_BASE (MVEBU_REGS_BASE + 0x512000)
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+#define PLAT_MARVELL_UART_CLK_IN_HZ 200000000
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#define PLAT_MARVELL_BL31_RUN_UART_BASE PLAT_MARVELL_BOOT_UART_BASE
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#define PLAT_MARVELL_BL31_RUN_UART_CLK_IN_HZ PLAT_MARVELL_BOOT_UART_CLK_IN_HZ
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--- a/plat/marvell/armada/common/aarch64/marvell_helpers.S
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+++ b/plat/marvell/armada/common/aarch64/marvell_helpers.S
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@@ -63,8 +63,8 @@ endfunc plat_marvell_calc_core_pos
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* ---------------------------------------------
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*/
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func plat_crash_console_init
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- mov_imm x0, PLAT_MARVELL_CRASH_UART_BASE
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- mov_imm x1, PLAT_MARVELL_CRASH_UART_CLK_IN_HZ
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+ mov_imm x0, PLAT_MARVELL_UART_BASE
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+ mov_imm x1, PLAT_MARVELL_UART_CLK_IN_HZ
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mov_imm x2, MARVELL_CONSOLE_BAUDRATE
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#ifdef PLAT_a3700
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b console_a3700_core_init
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@@ -81,7 +81,7 @@ endfunc plat_crash_console_init
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* ---------------------------------------------
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*/
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func plat_crash_console_putc
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- mov_imm x1, PLAT_MARVELL_CRASH_UART_BASE
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+ mov_imm x1, PLAT_MARVELL_UART_BASE
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#ifdef PLAT_a3700
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b console_a3700_core_putc
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@@ -99,7 +99,7 @@ endfunc plat_crash_console_putc
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* ---------------------------------------------
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*/
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func plat_crash_console_flush
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- mov_imm x0, PLAT_MARVELL_CRASH_UART_BASE
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+ mov_imm x0, PLAT_MARVELL_UART_BASE
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#ifdef PLAT_a3700
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b console_a3700_core_flush
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#else
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--- a/plat/marvell/armada/common/marvell_console.c
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+++ b/plat/marvell/armada/common/marvell_console.c
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@@ -31,8 +31,8 @@ static console_t marvell_runtime_console
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void marvell_console_boot_init(void)
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{
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int rc =
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- console_marvell_register(PLAT_MARVELL_BOOT_UART_BASE,
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- PLAT_MARVELL_BOOT_UART_CLK_IN_HZ,
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+ console_marvell_register(PLAT_MARVELL_UART_BASE,
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+ PLAT_MARVELL_UART_CLK_IN_HZ,
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MARVELL_CONSOLE_BAUDRATE,
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&marvell_boot_console);
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if (rc == 0) {
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@@ -58,8 +58,8 @@ void marvell_console_boot_end(void)
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void marvell_console_runtime_init(void)
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{
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int rc =
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- console_marvell_register(PLAT_MARVELL_BOOT_UART_BASE,
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- PLAT_MARVELL_BOOT_UART_CLK_IN_HZ,
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+ console_marvell_register(PLAT_MARVELL_UART_BASE,
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+ PLAT_MARVELL_UART_CLK_IN_HZ,
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MARVELL_CONSOLE_BAUDRATE,
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&marvell_runtime_console);
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if (rc == 0)
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@ -0,0 +1,177 @@
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From 5a91c439cbeb1f64b8b9830de91efad5113d3c89 Mon Sep 17 00:00:00 2001
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From: =?UTF-8?q?Pali=20Roh=C3=A1r?= <pali@kernel.org>
|
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Date: Fri, 14 May 2021 15:52:11 +0200
|
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Subject: [PATCH] fix(plat/marvell/a3720/uart): fix UART parent clock rate
|
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determination
|
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MIME-Version: 1.0
|
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
|
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|
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The UART code for the A3K platform assumes that UART parent clock rate
|
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is always 25 MHz. This is incorrect, because the xtal clock can also run
|
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at 40 MHz (this is board specific).
|
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|
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The frequency of the xtal clock is determined by a value on a strapping
|
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pin during SOC reset. The code to determine this frequency is already in
|
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A3K's comphy driver.
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|
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Move the get_ref_clk() function from the comphy driver to a separate
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file and use it for UART parent clock rate determination.
|
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|
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Signed-off-by: Pali Rohár <pali@kernel.org>
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Change-Id: I8bb18a2d020ef18fe65aa06ffa4ab205c71be92e
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---
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drivers/marvell/comphy/phy-comphy-3700.c | 24 +------------
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.../marvell/armada/a3k/common/plat_marvell.h | 2 ++
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.../marvell/armada/a3k/common/a3700_common.mk | 1 +
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.../armada/a3k/common/aarch64/a3700_clock.S | 35 +++++++++++++++++++
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.../armada/a3k/common/include/platform_def.h | 1 -
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.../armada/common/aarch64/marvell_helpers.S | 10 +++++-
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plat/marvell/armada/common/marvell_console.c | 1 +
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7 files changed, 49 insertions(+), 25 deletions(-)
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create mode 100644 plat/marvell/armada/a3k/common/aarch64/a3700_clock.S
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|
||||
--- a/drivers/marvell/comphy/phy-comphy-3700.c
|
||||
+++ b/drivers/marvell/comphy/phy-comphy-3700.c
|
||||
@@ -14,6 +14,7 @@
|
||||
|
||||
#include <mvebu.h>
|
||||
#include <mvebu_def.h>
|
||||
+#include <plat_marvell.h>
|
||||
|
||||
#include "phy-comphy-3700.h"
|
||||
#include "phy-comphy-common.h"
|
||||
@@ -29,15 +30,6 @@
|
||||
#define USB3_GBE1_PHY (MVEBU_REGS_BASE + 0x5C000)
|
||||
#define COMPHY_SD_ADDR (MVEBU_REGS_BASE + 0x1F000)
|
||||
|
||||
-/*
|
||||
- * Below address in used only for reading, therefore no problem with concurrent
|
||||
- * Linux access.
|
||||
- */
|
||||
-#define MVEBU_TEST_PIN_LATCH_N (MVEBU_NB_GPIO_REG_BASE + 0x8)
|
||||
- #define MVEBU_XTAL_MODE_MASK BIT(9)
|
||||
- #define MVEBU_XTAL_MODE_OFFS 9
|
||||
- #define MVEBU_XTAL_CLOCK_25MHZ 0x0
|
||||
-
|
||||
struct sgmii_phy_init_data_fix {
|
||||
uint16_t addr;
|
||||
uint16_t value;
|
||||
@@ -125,20 +117,6 @@ static uint16_t sgmii_phy_init[512] = {
|
||||
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000 /*1F8 */
|
||||
};
|
||||
|
||||
-/* returns reference clock in MHz (25 or 40) */
|
||||
-static uint32_t get_ref_clk(void)
|
||||
-{
|
||||
- uint32_t val;
|
||||
-
|
||||
- val = (mmio_read_32(MVEBU_TEST_PIN_LATCH_N) & MVEBU_XTAL_MODE_MASK) >>
|
||||
- MVEBU_XTAL_MODE_OFFS;
|
||||
-
|
||||
- if (val == MVEBU_XTAL_CLOCK_25MHZ)
|
||||
- return 25;
|
||||
- else
|
||||
- return 40;
|
||||
-}
|
||||
-
|
||||
/* PHY selector configures with corresponding modes */
|
||||
static void mvebu_a3700_comphy_set_phy_selector(uint8_t comphy_index,
|
||||
uint32_t comphy_mode)
|
||||
--- a/include/plat/marvell/armada/a3k/common/plat_marvell.h
|
||||
+++ b/include/plat/marvell/armada/a3k/common/plat_marvell.h
|
||||
@@ -100,4 +100,6 @@ void plat_marvell_interconnect_enter_coh
|
||||
|
||||
const mmap_region_t *plat_marvell_get_mmap(void);
|
||||
|
||||
+uint32_t get_ref_clk(void);
|
||||
+
|
||||
#endif /* PLAT_MARVELL_H */
|
||||
--- a/plat/marvell/armada/a3k/common/a3700_common.mk
|
||||
+++ b/plat/marvell/armada/a3k/common/a3700_common.mk
|
||||
@@ -38,6 +38,7 @@ PLAT_INCLUDES := -I$(PLAT_FAMILY_BASE)/
|
||||
-I$/drivers/arm/gic/common/
|
||||
|
||||
PLAT_BL_COMMON_SOURCES := $(PLAT_COMMON_BASE)/aarch64/a3700_common.c \
|
||||
+ $(PLAT_COMMON_BASE)/aarch64/a3700_clock.S \
|
||||
$(MARVELL_DRV_BASE)/uart/a3700_console.S
|
||||
|
||||
BL1_SOURCES += $(PLAT_COMMON_BASE)/aarch64/plat_helpers.S \
|
||||
--- /dev/null
|
||||
+++ b/plat/marvell/armada/a3k/common/aarch64/a3700_clock.S
|
||||
@@ -0,0 +1,35 @@
|
||||
+/*
|
||||
+ * Copyright (C) 2018 Marvell International Ltd.
|
||||
+ *
|
||||
+ * SPDX-License-Identifier: BSD-3-Clause
|
||||
+ * https://spdx.org/licenses
|
||||
+ */
|
||||
+
|
||||
+#include <asm_macros.S>
|
||||
+#include <platform_def.h>
|
||||
+
|
||||
+/*
|
||||
+ * Below address in used only for reading, therefore no problem with concurrent
|
||||
+ * Linux access.
|
||||
+ */
|
||||
+#define MVEBU_TEST_PIN_LATCH_N (MVEBU_NB_GPIO_REG_BASE + 0x8)
|
||||
+ #define MVEBU_XTAL_MODE_MASK BIT(9)
|
||||
+
|
||||
+ /* -----------------------------------------------------
|
||||
+ * uint32_t get_ref_clk (void);
|
||||
+ *
|
||||
+ * returns reference clock in MHz (25 or 40)
|
||||
+ * -----------------------------------------------------
|
||||
+ */
|
||||
+.globl get_ref_clk
|
||||
+func get_ref_clk
|
||||
+ mov_imm x0, MVEBU_TEST_PIN_LATCH_N
|
||||
+ ldr w0, [x0]
|
||||
+ tst w0, #MVEBU_XTAL_MODE_MASK
|
||||
+ bne 40
|
||||
+ mov w0, #25
|
||||
+ ret
|
||||
+40:
|
||||
+ mov w0, #40
|
||||
+ ret
|
||||
+endfunc get_ref_clk
|
||||
--- a/plat/marvell/armada/a3k/common/include/platform_def.h
|
||||
+++ b/plat/marvell/armada/a3k/common/include/platform_def.h
|
||||
@@ -164,7 +164,6 @@
|
||||
* PL011 related constants
|
||||
*/
|
||||
#define PLAT_MARVELL_UART_BASE (MVEBU_REGS_BASE + 0x12000)
|
||||
-#define PLAT_MARVELL_UART_CLK_IN_HZ 25000000
|
||||
|
||||
#define PLAT_MARVELL_BL31_RUN_UART_BASE PLAT_MARVELL_BOOT_UART_BASE
|
||||
#define PLAT_MARVELL_BL31_RUN_UART_CLK_IN_HZ PLAT_MARVELL_BOOT_UART_CLK_IN_HZ
|
||||
--- a/plat/marvell/armada/common/aarch64/marvell_helpers.S
|
||||
+++ b/plat/marvell/armada/common/aarch64/marvell_helpers.S
|
||||
@@ -63,8 +63,16 @@ endfunc plat_marvell_calc_core_pos
|
||||
* ---------------------------------------------
|
||||
*/
|
||||
func plat_crash_console_init
|
||||
- mov_imm x0, PLAT_MARVELL_UART_BASE
|
||||
+#ifdef PLAT_a3700
|
||||
+ mov x1, x30
|
||||
+ bl get_ref_clk
|
||||
+ mov x30, x1
|
||||
+ mov_imm x1, 1000000
|
||||
+ mul x1, x0, x1
|
||||
+#else
|
||||
mov_imm x1, PLAT_MARVELL_UART_CLK_IN_HZ
|
||||
+#endif
|
||||
+ mov_imm x0, PLAT_MARVELL_UART_BASE
|
||||
mov_imm x2, MARVELL_CONSOLE_BAUDRATE
|
||||
#ifdef PLAT_a3700
|
||||
b console_a3700_core_init
|
||||
--- a/plat/marvell/armada/common/marvell_console.c
|
||||
+++ b/plat/marvell/armada/common/marvell_console.c
|
||||
@@ -14,6 +14,7 @@
|
||||
|
||||
#ifdef PLAT_a3700
|
||||
#include <drivers/marvell/uart/a3700_console.h>
|
||||
+#define PLAT_MARVELL_UART_CLK_IN_HZ (get_ref_clk() * 1000000)
|
||||
#define console_marvell_register console_a3700_register
|
||||
#else
|
||||
#include <drivers/ti/uart/uart_16550.h>
|
||||
Loading…
Reference in New Issue