mirror
/
openwrt
mirror of https://git.openwrt.org/openwrt/openwrt.git
1
0
Fork 0
Code Releases Activity

ramips: dts: rt3050: reset FE and ESW cores together 

Failing to do so will cause the DMA engine to not initialize properly
and fail to forward packets between them, and in some cases will cause
spurious transmission with size exceeding allowed packet size, causing a
kernel panic.

This is behaviour of downstream driver as well, however I
haven't observed bug reports about this SoC in the wild, so this
commit's purpose is to align this chip with all other SoC's - MT7620
were already using this arrangement.

Fixes: 60fadae62b ("ramips: ethernet: ralink: move reset of the esw into the esw instead of fe")
Signed-off-by: Lech Perczak <lech.perczak@gmail.com>

(cherry picked from commit c5a399f372)
Signed-off-by: Lech Perczak <lech.perczak@gmail.com>
This commit is contained in:
Lech Perczak 2023-12-12 00:22:04 +01:00
parent 37ed4c0ec2
commit 0c84a15288
1 changed files with 4 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
target/linux/ramips/dts/rt3050.dtsi
View File

@ -306,8 +306,8 @@
compatible = "ralink,rt3050-eth";
reg = <0x10100000 0x10000>;
resets = <&rstctrl 21>;
reset-names = "fe";
resets = <&rstctrl 21>, <&rstctrl 23>;
reset-names = "fe", "esw";
interrupt-parent = <&cpuintc>;
interrupts = <5>;
@ -319,8 +319,8 @@
compatible = "ralink,rt3050-esw";
reg = <0x10110000 0x8000>;
resets = <&rstctrl 23 &rstctrl 24>;
reset-names = "esw", "ephy";
resets = <&rstctrl 24>;
reset-names = "ephy";
interrupt-parent = <&intc>;
interrupts = <17>;