mirror
/
openwrt
mirror of https://git.openwrt.org/openwrt/openwrt.git
1
0
Fork 0
Code Releases Activity

ramips: dts: rt3050: reset FE and ESW cores together 

Failing to do so will cause the DMA engine to not initialize properly
and fail to forward packets between them, and in some cases will cause
spurious transmission with size exceeding allowed packet size, causing a
kernel panic.

This is behaviour of downstream driver as well, however I
haven't observed bug reports about this SoC in the wild, so this
commit's purpose is to align this chip with all other SoC's - MT7620
were already using this arrangement.

Fixes: 60fadae62b ("ramips: ethernet: ralink: move reset of the esw into the esw instead of fe")
Signed-off-by: Lech Perczak <lech.perczak@gmail.com>
This commit is contained in:
Lech Perczak 2023-12-12 00:22:04 +01:00 committed by Hauke Mehrtens
parent 8d75b1de0f
commit c5a399f372
1 changed files with 4 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
target/linux/ramips/dts/rt3050.dtsi
View File

@ -301,8 +301,8 @@
clocks = <&sysc 11>;
resets = <&sysc 21>;
reset-names = "fe";
resets = <&sysc 21>, <&sysc 23>;
reset-names = "fe", "esw";
interrupt-parent = <&cpuintc>;
interrupts = <5>;
@ -314,8 +314,8 @@
compatible = "ralink,rt3050-esw";
reg = <0x10110000 0x8000>;
resets = <&sysc 23>, <&sysc 24>;
reset-names = "esw", "ephy";
resets = <&sysc 24>;
reset-names = "ephy";
interrupt-parent = <&intc>;
interrupts = <17>;