forked from freifunk-franken/firmware
410 lines
9.2 KiB
Diff
410 lines
9.2 KiB
Diff
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From 8b44a21163ac6504dabc3a6dda8c53388913d471 Mon Sep 17 00:00:00 2001
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From: =?UTF-8?q?Fabian=20Bl=C3=A4se?= <fabian@blaese.de>
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Date: Fri, 20 Oct 2023 22:56:53 +0200
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Subject: [PATCH] Add support for SolidRun CN9130 ClearFog Base
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---
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.../arm64/boot/dts/marvell/cn9130-cf-base.dts | 368 ++++++++++++++++++
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target/linux/mvebu/image/cortexa72.mk | 10 +
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2 files changed, 378 insertions(+)
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create mode 100644 target/linux/mvebu/files/arch/arm64/boot/dts/marvell/cn9130-cf-base.dts
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diff --git a/target/linux/mvebu/files/arch/arm64/boot/dts/marvell/cn9130-cf-base.dts b/target/linux/mvebu/files/arch/arm64/boot/dts/marvell/cn9130-cf-base.dts
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new file mode 100644
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index 0000000000..2010541f01
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--- /dev/null
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+++ b/target/linux/mvebu/files/arch/arm64/boot/dts/marvell/cn9130-cf-base.dts
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@@ -0,0 +1,368 @@
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+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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+/*
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+ * Copyright SolidRun Ltd.
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+ *
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+ * Device tree for the CN9130 based SOM.
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+ */
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+
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+#include "cn9130.dtsi"
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+
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+#include <dt-bindings/gpio/gpio.h>
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+
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+/ {
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+ model = "SolidRun CN9130 based SOM Clearfog Base";
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+ compatible = "solidrun,cn9130-cf-pro", "marvell,cn9130", "marvell,armada-ap807-quad",
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+ "marvell,armada-ap807";
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+
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+ chosen {
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+ stdout-path = "serial0:115200n8";
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+ };
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+
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+ aliases {
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+ gpio1 = &cp0_gpio1;
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+ gpio2 = &cp0_gpio2;
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+ i2c0 = &cp0_i2c0;
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+ ethernet0 = &cp0_eth0;
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+ ethernet1 = &cp0_eth1;
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+ ethernet2 = &cp0_eth2;
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+ spi1 = &cp0_spi0;
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+ spi2 = &cp0_spi1;
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+ };
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+
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+ memory@0 {
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+ device_type = "memory";
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+ reg = <0x0 0x0 0x0 0x80000000>;
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+ };
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+ v_3_3: regulator-3-3v {
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+ compatible = "regulator-fixed";
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+ regulator-name = "v_3_3";
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+ regulator-min-microvolt = <3300000>;
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+ regulator-max-microvolt = <3300000>;
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+ regulator-always-on;
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+ status = "okay";
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+ };
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+ ap0_reg_sd_vccq: ap0-sd_-ccq@0 {
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+ compatible = "regulator-gpio";
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+ regulator-name = "ap0_sd_vccq";
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+ regulator-min-microvolt = <1800000>;
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+ regulator-max-microvolt = <1800000>;
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+ states = <1800000 0x1 3300000 0x0>;
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+ };
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+
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+ cp0_reg_usb3_vbus0: cp0-usb3-vbus@0 {
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+ compatible = "regulator-fixed";
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+ regulator-name = "cp0-xhci0-vbus";
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+ regulator-min-microvolt = <5000000>;
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+ regulator-max-microvolt = <5000000>;
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+ enable-active-high;
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+ };
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+
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+ cp0_usb3_0_phy0: cp0-usb3-phy@0 {
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+ compatible = "usb-nop-xceiv";
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+ vcc-supply = <&cp0_reg_usb3_vbus0>;
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+ };
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+
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+ cp0_reg_usb3_vbus1: cp0-usb3-vbus@1 {
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+ compatible = "regulator-fixed";
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+ regulator-name = "cp0-xhci1-vbus";
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+ regulator-min-microvolt = <5000000>;
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+ regulator-max-microvolt = <5000000>;
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+ enable-active-high;
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+ };
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+
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+ cp0_usb3_0_phy1: cp0-usb3-phy@1 {
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+ compatible = "usb-nop-xceiv";
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+ vcc-supply = <&cp0_reg_usb3_vbus1>;
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+ };
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+
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+ cp0_reg_sd_vccq: cp0-sd-vccq@0 {
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+ compatible = "regulator-gpio";
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+ regulator-name = "cp0_sd_vccq";
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+ regulator-min-microvolt = <1800000>;
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+ regulator-max-microvolt = <3300000>;
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+ states = <1800000 0x1
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+ 3300000 0x0>;
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+ };
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+
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+ cp0_reg_sd_vcc: cp0-sd-vcc@0 {
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+ compatible = "regulator-fixed";
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+ regulator-name = "cp0_sd_vcc";
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+ regulator-min-microvolt = <3300000>;
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+ regulator-max-microvolt = <3300000>;
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+ enable-active-high;
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+ regulator-always-on;
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+ };
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+
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+ cp0_sfp_eth0: sfp-eth@0 {
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+ compatible = "sff,sfp";
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+ i2c-bus = <&cp0_i2c1>;
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+ los-gpio = <&expander0 12 GPIO_ACTIVE_HIGH>;
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+ mod-def0-gpio = <&expander0 15 GPIO_ACTIVE_LOW>;
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+ tx-disable-gpio = <&expander0 14 GPIO_ACTIVE_HIGH>;
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+ tx-fault-gpio = <&expander0 13 GPIO_ACTIVE_HIGH>;
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+ maximum-power-milliwatt = <2000>;
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+ };
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+};
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+
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+&uart0 {
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+ status = "okay";
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+};
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+
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+/* on-board eMMC */
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+&ap_sdhci0 {
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+ pinctrl-names = "default";
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+ bus-width = <8>;
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+ vqmmc-supply = <&ap0_reg_sd_vccq>;
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+ status = "okay";
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+};
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+
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+&cp0_crypto {
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+ status = "disabled";
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+};
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+
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+&cp0_ethernet {
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+ status = "okay";
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+};
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+
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+&cp0_gpio1 {
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+ status = "okay";
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+};
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+
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+&cp0_gpio2 {
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+ status = "okay";
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+};
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+
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+/* EEPROM */
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+&cp0_i2c0 {
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+ status = "okay";
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&cp0_i2c0_pins>;
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+ clock-frequency = <100000>;
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+
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+ /*
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+ * PCA9655 GPIO expander, up to 1MHz clock.
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+ * 0-CON3 CLKREQ#
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+ * 1-CON3 PERST#
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+ * 2-CON2 PERST#
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+ * 3-CON3 W_DISABLE
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+ * 4-CON2 CLKREQ#
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+ * 5-USB3 overcurrent
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+ * 6-USB3 power
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+ * 7-CON2 W_DISABLE
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+ * 8-JP4 P1
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+ * 9-JP4 P4
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+ * 10-JP4 P5
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+ * 11-m.2 DEVSLP
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+ * 12-SFP_LOS
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+ * 13-SFP_TX_FAULT
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+ * 14-SFP_TX_DISABLE
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+ * 15-SFP_MOD_DEF0
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+ */
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+ expander0: gpio-expander@20 {
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+ /*
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+ * This is how it should be:
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+ * compatible = "onnn,pca9655", "nxp,pca9555";
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+ * but you can't do this because of the way I2C works.
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+ */
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+ compatible = "nxp,pca9555";
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+ gpio-controller;
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+ #gpio-cells = <2>;
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+ reg = <0x20>;
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+
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+ pcie1-0-clkreq {
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+ gpio-hog;
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+ gpios = <0 GPIO_ACTIVE_LOW>;
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+ input;
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+ line-name = "pcie1.0-clkreq";
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+ };
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+ pcie1-0-w-disable {
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+ gpio-hog;
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+ gpios = <3 GPIO_ACTIVE_LOW>;
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+ output-low;
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+ line-name = "pcie1.0-w-disable";
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+ };
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+ usb3-ilimit {
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+ gpio-hog;
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+ gpios = <5 GPIO_ACTIVE_LOW>;
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+ input;
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+ line-name = "usb3-current-limit";
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+ };
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+ usb3-power {
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+ gpio-hog;
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+ gpios = <6 GPIO_ACTIVE_HIGH>;
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+ output-high;
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+ line-name = "usb3-power";
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+ };
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+ m2-devslp {
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+ gpio-hog;
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+ gpios = <11 GPIO_ACTIVE_HIGH>;
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+ output-low;
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+ line-name = "m.2 devslp";
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+ };
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+ };
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+
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+ /* The MCP3021 supports standard and fast modes */
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+ mikrobus_adc: mcp3021@4c {
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+ compatible = "microchip,mcp3021";
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+ reg = <0x4c>;
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+ };
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+
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+ /* EEPROM on the SOM */
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+ eeprom@53 {
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+ compatible = "atmel,24c02";
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+ reg = <0x53>;
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+ pagesize = <16>;
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+ };
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+};
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+
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+/* I2C Master */
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+&cp0_i2c1 {
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+ status = "okay";
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+ clock-frequency = <100000>;
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&cp0_i2c1_pins>;
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+};
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+
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+&cp0_gpio1 {
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+ /* Release switch reset */
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+ phy-reset {
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+ gpio-hog;
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+ gpios = <27 GPIO_ACTIVE_HIGH>;
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+ output-high;
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+ };
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+};
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+
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+&cp0_mdio {
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+ status = "okay";
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+ phy0: ethernet-phy@0 {
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+ /* Green led blinks on activity, Orange LED on link */
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+ marvell,reg-init = <3 16 0 0x0064>;
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+ reg = <0>;
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+ };
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+ phy1: ethernet-phy@1 {
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+ /* Green led blinks on activity, Orange LED on link */
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+ marvell,reg-init = <3 16 0 0x0064>;
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+ reg = <1>;
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+ };
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+};
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+
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+/* SRDS #0 - SATA on M.2 connector */
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+&cp0_sata0 {
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+ status = "okay";
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+};
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+
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+/* SRDS #1 - USB 3.0 host */
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+&cp0_usb3_0 {
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+ status = "okay";
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+ usb-phy = <&cp0_usb3_0_phy0>;
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+ phy-names = "usb";
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+};
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+
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+/* SRDS #2 - SFP+ 10GE */
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+&cp0_eth0 {
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+ status = "okay";
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+ phy-mode = "10gbase-r";
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+ phys = <&cp0_comphy2 0>;
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+ managed = "in-band-status";
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+ sfp = <&cp0_sfp_eth0>;
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+};
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+
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+/* SRDS #3 - SGMII 1GE on carrier board */
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+&cp0_eth1 {
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+ status = "okay";
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+ phys = <&cp0_comphy3 1>;
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+ phy = <&phy1>;
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+ managed = "in-band-status";
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+ phy-mode = "sgmii";
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+};
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+
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+/* SRDS #4 - USB 3.0 host on M.2 connector */
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+&cp0_usb3_1 {
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+ status = "okay";
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+ usb-phy = <&cp0_usb3_0_phy1>;
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+ phy-names = "usb";
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+};
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+
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+/* SRDS #5 - mini PCIe slot */
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+&cp0_pcie2 {
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+ status = "okay";
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+ phys = <&cp0_comphy5 2>;
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+ num-lanes = <1>;
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+ reset-gpios = <&expander0 1 GPIO_ACTIVE_LOW>;
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+};
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+
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+/* GE PHY RGMII */
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+&cp0_eth2 {
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+ status = "okay";
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+ phy = <&phy0>;
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+ phy-mode = "rgmii-id";
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+ pinctrl-0 = <&cp0_ge2_rgmii_pins>;
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+};
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+
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+&cp0_sdhci0 {
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+ status = "okay";
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&cp0_sdhci_pins
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+ &cp0_sdhci_cd_pins>;
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+ bus-width = <4>;
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+ cd-gpios = <&cp0_gpio2 11 GPIO_ACTIVE_LOW>;
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+ no-1-8-v;
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+ vqmmc-supply = <&v_3_3>;
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+ vmmc-supply = <&v_3_3>;
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+};
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+
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+&cp0_spi1 {
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+ status = "okay";
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&cp0_spi1_pins>;
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+ reg = <0x700680 0x50>;
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+ spi-flash@0 {
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+ #address-cells = <0x1>;
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+ #size-cells = <0x1>;
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+ compatible = "jedec,spi-nor";
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+ reg = <0x0>;
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+ spi-max-frequency = <10000000>;
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+ };
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+ spi-flash@1 {
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+ #address-cells = <0x1>;
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+ #size-cells = <0x1>;
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+ compatible = "jedec,spi-nor";
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+ reg = <0x1>;
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+ /* On carrier MUX does not allow higher frequencies */
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+ spi-max-frequency = <20000000>;
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+ };
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+};
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+
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+&cp0_syscon0 {
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+ cp0_pinctrl: pinctrl {
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+ compatible = "marvell,cp115-standalone-pinctrl";
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+ cp0_i2c0_pins: cp0-i2c-pins-0 {
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+ marvell,pins = "mpp37", "mpp38";
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+ marvell,function = "i2c0";
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+ };
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+ cp0_i2c1_pins: cp0-i2c-pins-1 {
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+ marvell,pins = "mpp35", "mpp36";
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+ marvell,function = "i2c1";
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+ };
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+ cp0_ge2_rgmii_pins: cp0-ge-rgmii-pins-0 {
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+ marvell,pins = "mpp44", "mpp45", "mpp46",
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+ "mpp47", "mpp48", "mpp49",
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+ "mpp50", "mpp51", "mpp52",
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+ "mpp53", "mpp54", "mpp55";
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+ marvell,function = "ge1";
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+ };
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+ cp0_sdhci_cd_pins: cp0-sdhci-cd-pins-0 {
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+ marvell,pins = "mpp43";
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+ marvell,function = "sdio";
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+ };
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+ cp0_sdhci_pins: cp0-sdhi-pins-0 {
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+ marvell,pins = "mpp56", "mpp57", "mpp58",
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+ "mpp59", "mpp60", "mpp61";
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+ marvell,function = "sdio";
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+ };
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+ cp0_spi1_pins: cp0-spi-pins-1 {
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+ marvell,pins = "mpp12", "mpp13", "mpp14", "mpp15", "mpp16";
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+ marvell,function = "spi1";
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+ };
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+ };
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+};
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diff --git a/target/linux/mvebu/image/cortexa72.mk b/target/linux/mvebu/image/cortexa72.mk
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index c4fb76f4f5..e342014e1a 100644
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--- a/target/linux/mvebu/image/cortexa72.mk
|
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+++ b/target/linux/mvebu/image/cortexa72.mk
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@@ -68,6 +68,16 @@ define Device/iei_puzzle-m902
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endef
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TARGET_DEVICES += iei_puzzle-m902
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|
|
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+define Device/solidrun_cn9130-cf-base
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||
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+ $(call Device/Default-arm64)
|
||
|
+ DEVICE_VENDOR := SolidRun
|
||
|
+ DEVICE_MODEL := ClearFog
|
||
|
+ DEVICE_VARIANT := CN9130-Base
|
||
|
+ DEVICE_DTS := cn9130-cf-base
|
||
|
+ SUPPORTED_DEVICES := solidrun,cn9130-cf-base
|
||
|
+endef
|
||
|
+TARGET_DEVICES += solidrun_cn9130-cf-base
|
||
|
+
|
||
|
define Device/solidrun_cn9130-cf-pro
|
||
|
$(call Device/Default-arm64)
|
||
|
DEVICE_VENDOR := SolidRun
|
||
|
--
|
||
|
2.42.0
|
||
|
|