forked from freifunk-franken/firmware
Add support for SolidRun CN9130 ClearFog Base
This commit is contained in:
parent
503f9c4fe1
commit
915401b6f9
|
|
@ -3,4 +3,5 @@ subtarget=cortexa72
|
|||
|
||||
images=(
|
||||
"openwrt-mvebu-cortexa72-solidrun_cn9130-cf-pro-squashfs*"
|
||||
"openwrt-mvebu-cortexa72-solidrun_cn9130-cf-base-squashfs*"
|
||||
)
|
||||
|
|
|
|||
|
|
@ -3,7 +3,9 @@
|
|||
#
|
||||
CONFIG_TARGET_mvebu=y
|
||||
CONFIG_TARGET_mvebu_cortexa72=y
|
||||
CONFIG_TARGET_mvebu_cortexa72_DEVICE_solidrun_cn9130-cf-pro=y
|
||||
CONFIG_TARGET_MULTI_PROFILE=y
|
||||
CONFIG_TARGET_DEVICE_mvebu_cortexa72_DEVICE_solidrun_cn9130-cf-base=y
|
||||
CONFIG_TARGET_DEVICE_mvebu_cortexa72_DEVICE_solidrun_cn9130-cf-pro=y
|
||||
CONFIG_KERNEL_KEXEC=y
|
||||
CONFIG_PACKAGE_ca-bundle=y
|
||||
CONFIG_PACKAGE_dnsmasq=y
|
||||
|
|
|
|||
|
|
@ -0,0 +1,409 @@
|
|||
From 8b44a21163ac6504dabc3a6dda8c53388913d471 Mon Sep 17 00:00:00 2001
|
||||
From: =?UTF-8?q?Fabian=20Bl=C3=A4se?= <fabian@blaese.de>
|
||||
Date: Fri, 20 Oct 2023 22:56:53 +0200
|
||||
Subject: [PATCH] Add support for SolidRun CN9130 ClearFog Base
|
||||
|
||||
---
|
||||
.../arm64/boot/dts/marvell/cn9130-cf-base.dts | 368 ++++++++++++++++++
|
||||
target/linux/mvebu/image/cortexa72.mk | 10 +
|
||||
2 files changed, 378 insertions(+)
|
||||
create mode 100644 target/linux/mvebu/files/arch/arm64/boot/dts/marvell/cn9130-cf-base.dts
|
||||
|
||||
diff --git a/target/linux/mvebu/files/arch/arm64/boot/dts/marvell/cn9130-cf-base.dts b/target/linux/mvebu/files/arch/arm64/boot/dts/marvell/cn9130-cf-base.dts
|
||||
new file mode 100644
|
||||
index 0000000000..2010541f01
|
||||
--- /dev/null
|
||||
+++ b/target/linux/mvebu/files/arch/arm64/boot/dts/marvell/cn9130-cf-base.dts
|
||||
@@ -0,0 +1,368 @@
|
||||
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
+/*
|
||||
+ * Copyright SolidRun Ltd.
|
||||
+ *
|
||||
+ * Device tree for the CN9130 based SOM.
|
||||
+ */
|
||||
+
|
||||
+#include "cn9130.dtsi"
|
||||
+
|
||||
+#include <dt-bindings/gpio/gpio.h>
|
||||
+
|
||||
+/ {
|
||||
+ model = "SolidRun CN9130 based SOM Clearfog Base";
|
||||
+ compatible = "solidrun,cn9130-cf-pro", "marvell,cn9130", "marvell,armada-ap807-quad",
|
||||
+ "marvell,armada-ap807";
|
||||
+
|
||||
+ chosen {
|
||||
+ stdout-path = "serial0:115200n8";
|
||||
+ };
|
||||
+
|
||||
+ aliases {
|
||||
+ gpio1 = &cp0_gpio1;
|
||||
+ gpio2 = &cp0_gpio2;
|
||||
+ i2c0 = &cp0_i2c0;
|
||||
+ ethernet0 = &cp0_eth0;
|
||||
+ ethernet1 = &cp0_eth1;
|
||||
+ ethernet2 = &cp0_eth2;
|
||||
+ spi1 = &cp0_spi0;
|
||||
+ spi2 = &cp0_spi1;
|
||||
+ };
|
||||
+
|
||||
+ memory@0 {
|
||||
+ device_type = "memory";
|
||||
+ reg = <0x0 0x0 0x0 0x80000000>;
|
||||
+ };
|
||||
+ v_3_3: regulator-3-3v {
|
||||
+ compatible = "regulator-fixed";
|
||||
+ regulator-name = "v_3_3";
|
||||
+ regulator-min-microvolt = <3300000>;
|
||||
+ regulator-max-microvolt = <3300000>;
|
||||
+ regulator-always-on;
|
||||
+ status = "okay";
|
||||
+ };
|
||||
+ ap0_reg_sd_vccq: ap0-sd_-ccq@0 {
|
||||
+ compatible = "regulator-gpio";
|
||||
+ regulator-name = "ap0_sd_vccq";
|
||||
+ regulator-min-microvolt = <1800000>;
|
||||
+ regulator-max-microvolt = <1800000>;
|
||||
+ states = <1800000 0x1 3300000 0x0>;
|
||||
+ };
|
||||
+
|
||||
+ cp0_reg_usb3_vbus0: cp0-usb3-vbus@0 {
|
||||
+ compatible = "regulator-fixed";
|
||||
+ regulator-name = "cp0-xhci0-vbus";
|
||||
+ regulator-min-microvolt = <5000000>;
|
||||
+ regulator-max-microvolt = <5000000>;
|
||||
+ enable-active-high;
|
||||
+ };
|
||||
+
|
||||
+ cp0_usb3_0_phy0: cp0-usb3-phy@0 {
|
||||
+ compatible = "usb-nop-xceiv";
|
||||
+ vcc-supply = <&cp0_reg_usb3_vbus0>;
|
||||
+ };
|
||||
+
|
||||
+ cp0_reg_usb3_vbus1: cp0-usb3-vbus@1 {
|
||||
+ compatible = "regulator-fixed";
|
||||
+ regulator-name = "cp0-xhci1-vbus";
|
||||
+ regulator-min-microvolt = <5000000>;
|
||||
+ regulator-max-microvolt = <5000000>;
|
||||
+ enable-active-high;
|
||||
+ };
|
||||
+
|
||||
+ cp0_usb3_0_phy1: cp0-usb3-phy@1 {
|
||||
+ compatible = "usb-nop-xceiv";
|
||||
+ vcc-supply = <&cp0_reg_usb3_vbus1>;
|
||||
+ };
|
||||
+
|
||||
+ cp0_reg_sd_vccq: cp0-sd-vccq@0 {
|
||||
+ compatible = "regulator-gpio";
|
||||
+ regulator-name = "cp0_sd_vccq";
|
||||
+ regulator-min-microvolt = <1800000>;
|
||||
+ regulator-max-microvolt = <3300000>;
|
||||
+ states = <1800000 0x1
|
||||
+ 3300000 0x0>;
|
||||
+ };
|
||||
+
|
||||
+ cp0_reg_sd_vcc: cp0-sd-vcc@0 {
|
||||
+ compatible = "regulator-fixed";
|
||||
+ regulator-name = "cp0_sd_vcc";
|
||||
+ regulator-min-microvolt = <3300000>;
|
||||
+ regulator-max-microvolt = <3300000>;
|
||||
+ enable-active-high;
|
||||
+ regulator-always-on;
|
||||
+ };
|
||||
+
|
||||
+ cp0_sfp_eth0: sfp-eth@0 {
|
||||
+ compatible = "sff,sfp";
|
||||
+ i2c-bus = <&cp0_i2c1>;
|
||||
+ los-gpio = <&expander0 12 GPIO_ACTIVE_HIGH>;
|
||||
+ mod-def0-gpio = <&expander0 15 GPIO_ACTIVE_LOW>;
|
||||
+ tx-disable-gpio = <&expander0 14 GPIO_ACTIVE_HIGH>;
|
||||
+ tx-fault-gpio = <&expander0 13 GPIO_ACTIVE_HIGH>;
|
||||
+ maximum-power-milliwatt = <2000>;
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&uart0 {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+/* on-board eMMC */
|
||||
+&ap_sdhci0 {
|
||||
+ pinctrl-names = "default";
|
||||
+ bus-width = <8>;
|
||||
+ vqmmc-supply = <&ap0_reg_sd_vccq>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&cp0_crypto {
|
||||
+ status = "disabled";
|
||||
+};
|
||||
+
|
||||
+&cp0_ethernet {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&cp0_gpio1 {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&cp0_gpio2 {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+/* EEPROM */
|
||||
+&cp0_i2c0 {
|
||||
+ status = "okay";
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&cp0_i2c0_pins>;
|
||||
+ clock-frequency = <100000>;
|
||||
+
|
||||
+ /*
|
||||
+ * PCA9655 GPIO expander, up to 1MHz clock.
|
||||
+ * 0-CON3 CLKREQ#
|
||||
+ * 1-CON3 PERST#
|
||||
+ * 2-CON2 PERST#
|
||||
+ * 3-CON3 W_DISABLE
|
||||
+ * 4-CON2 CLKREQ#
|
||||
+ * 5-USB3 overcurrent
|
||||
+ * 6-USB3 power
|
||||
+ * 7-CON2 W_DISABLE
|
||||
+ * 8-JP4 P1
|
||||
+ * 9-JP4 P4
|
||||
+ * 10-JP4 P5
|
||||
+ * 11-m.2 DEVSLP
|
||||
+ * 12-SFP_LOS
|
||||
+ * 13-SFP_TX_FAULT
|
||||
+ * 14-SFP_TX_DISABLE
|
||||
+ * 15-SFP_MOD_DEF0
|
||||
+ */
|
||||
+ expander0: gpio-expander@20 {
|
||||
+ /*
|
||||
+ * This is how it should be:
|
||||
+ * compatible = "onnn,pca9655", "nxp,pca9555";
|
||||
+ * but you can't do this because of the way I2C works.
|
||||
+ */
|
||||
+ compatible = "nxp,pca9555";
|
||||
+ gpio-controller;
|
||||
+ #gpio-cells = <2>;
|
||||
+ reg = <0x20>;
|
||||
+
|
||||
+ pcie1-0-clkreq {
|
||||
+ gpio-hog;
|
||||
+ gpios = <0 GPIO_ACTIVE_LOW>;
|
||||
+ input;
|
||||
+ line-name = "pcie1.0-clkreq";
|
||||
+ };
|
||||
+ pcie1-0-w-disable {
|
||||
+ gpio-hog;
|
||||
+ gpios = <3 GPIO_ACTIVE_LOW>;
|
||||
+ output-low;
|
||||
+ line-name = "pcie1.0-w-disable";
|
||||
+ };
|
||||
+ usb3-ilimit {
|
||||
+ gpio-hog;
|
||||
+ gpios = <5 GPIO_ACTIVE_LOW>;
|
||||
+ input;
|
||||
+ line-name = "usb3-current-limit";
|
||||
+ };
|
||||
+ usb3-power {
|
||||
+ gpio-hog;
|
||||
+ gpios = <6 GPIO_ACTIVE_HIGH>;
|
||||
+ output-high;
|
||||
+ line-name = "usb3-power";
|
||||
+ };
|
||||
+ m2-devslp {
|
||||
+ gpio-hog;
|
||||
+ gpios = <11 GPIO_ACTIVE_HIGH>;
|
||||
+ output-low;
|
||||
+ line-name = "m.2 devslp";
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ /* The MCP3021 supports standard and fast modes */
|
||||
+ mikrobus_adc: mcp3021@4c {
|
||||
+ compatible = "microchip,mcp3021";
|
||||
+ reg = <0x4c>;
|
||||
+ };
|
||||
+
|
||||
+ /* EEPROM on the SOM */
|
||||
+ eeprom@53 {
|
||||
+ compatible = "atmel,24c02";
|
||||
+ reg = <0x53>;
|
||||
+ pagesize = <16>;
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+/* I2C Master */
|
||||
+&cp0_i2c1 {
|
||||
+ status = "okay";
|
||||
+ clock-frequency = <100000>;
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&cp0_i2c1_pins>;
|
||||
+};
|
||||
+
|
||||
+&cp0_gpio1 {
|
||||
+ /* Release switch reset */
|
||||
+ phy-reset {
|
||||
+ gpio-hog;
|
||||
+ gpios = <27 GPIO_ACTIVE_HIGH>;
|
||||
+ output-high;
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&cp0_mdio {
|
||||
+ status = "okay";
|
||||
+ phy0: ethernet-phy@0 {
|
||||
+ /* Green led blinks on activity, Orange LED on link */
|
||||
+ marvell,reg-init = <3 16 0 0x0064>;
|
||||
+ reg = <0>;
|
||||
+ };
|
||||
+ phy1: ethernet-phy@1 {
|
||||
+ /* Green led blinks on activity, Orange LED on link */
|
||||
+ marvell,reg-init = <3 16 0 0x0064>;
|
||||
+ reg = <1>;
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+/* SRDS #0 - SATA on M.2 connector */
|
||||
+&cp0_sata0 {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+/* SRDS #1 - USB 3.0 host */
|
||||
+&cp0_usb3_0 {
|
||||
+ status = "okay";
|
||||
+ usb-phy = <&cp0_usb3_0_phy0>;
|
||||
+ phy-names = "usb";
|
||||
+};
|
||||
+
|
||||
+/* SRDS #2 - SFP+ 10GE */
|
||||
+&cp0_eth0 {
|
||||
+ status = "okay";
|
||||
+ phy-mode = "10gbase-r";
|
||||
+ phys = <&cp0_comphy2 0>;
|
||||
+ managed = "in-band-status";
|
||||
+ sfp = <&cp0_sfp_eth0>;
|
||||
+};
|
||||
+
|
||||
+/* SRDS #3 - SGMII 1GE on carrier board */
|
||||
+&cp0_eth1 {
|
||||
+ status = "okay";
|
||||
+ phys = <&cp0_comphy3 1>;
|
||||
+ phy = <&phy1>;
|
||||
+ managed = "in-band-status";
|
||||
+ phy-mode = "sgmii";
|
||||
+};
|
||||
+
|
||||
+/* SRDS #4 - USB 3.0 host on M.2 connector */
|
||||
+&cp0_usb3_1 {
|
||||
+ status = "okay";
|
||||
+ usb-phy = <&cp0_usb3_0_phy1>;
|
||||
+ phy-names = "usb";
|
||||
+};
|
||||
+
|
||||
+/* SRDS #5 - mini PCIe slot */
|
||||
+&cp0_pcie2 {
|
||||
+ status = "okay";
|
||||
+ phys = <&cp0_comphy5 2>;
|
||||
+ num-lanes = <1>;
|
||||
+ reset-gpios = <&expander0 1 GPIO_ACTIVE_LOW>;
|
||||
+};
|
||||
+
|
||||
+/* GE PHY RGMII */
|
||||
+&cp0_eth2 {
|
||||
+ status = "okay";
|
||||
+ phy = <&phy0>;
|
||||
+ phy-mode = "rgmii-id";
|
||||
+ pinctrl-0 = <&cp0_ge2_rgmii_pins>;
|
||||
+};
|
||||
+
|
||||
+&cp0_sdhci0 {
|
||||
+ status = "okay";
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&cp0_sdhci_pins
|
||||
+ &cp0_sdhci_cd_pins>;
|
||||
+ bus-width = <4>;
|
||||
+ cd-gpios = <&cp0_gpio2 11 GPIO_ACTIVE_LOW>;
|
||||
+ no-1-8-v;
|
||||
+ vqmmc-supply = <&v_3_3>;
|
||||
+ vmmc-supply = <&v_3_3>;
|
||||
+};
|
||||
+
|
||||
+&cp0_spi1 {
|
||||
+ status = "okay";
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&cp0_spi1_pins>;
|
||||
+ reg = <0x700680 0x50>;
|
||||
+ spi-flash@0 {
|
||||
+ #address-cells = <0x1>;
|
||||
+ #size-cells = <0x1>;
|
||||
+ compatible = "jedec,spi-nor";
|
||||
+ reg = <0x0>;
|
||||
+ spi-max-frequency = <10000000>;
|
||||
+ };
|
||||
+ spi-flash@1 {
|
||||
+ #address-cells = <0x1>;
|
||||
+ #size-cells = <0x1>;
|
||||
+ compatible = "jedec,spi-nor";
|
||||
+ reg = <0x1>;
|
||||
+ /* On carrier MUX does not allow higher frequencies */
|
||||
+ spi-max-frequency = <20000000>;
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&cp0_syscon0 {
|
||||
+ cp0_pinctrl: pinctrl {
|
||||
+ compatible = "marvell,cp115-standalone-pinctrl";
|
||||
+ cp0_i2c0_pins: cp0-i2c-pins-0 {
|
||||
+ marvell,pins = "mpp37", "mpp38";
|
||||
+ marvell,function = "i2c0";
|
||||
+ };
|
||||
+ cp0_i2c1_pins: cp0-i2c-pins-1 {
|
||||
+ marvell,pins = "mpp35", "mpp36";
|
||||
+ marvell,function = "i2c1";
|
||||
+ };
|
||||
+ cp0_ge2_rgmii_pins: cp0-ge-rgmii-pins-0 {
|
||||
+ marvell,pins = "mpp44", "mpp45", "mpp46",
|
||||
+ "mpp47", "mpp48", "mpp49",
|
||||
+ "mpp50", "mpp51", "mpp52",
|
||||
+ "mpp53", "mpp54", "mpp55";
|
||||
+ marvell,function = "ge1";
|
||||
+ };
|
||||
+ cp0_sdhci_cd_pins: cp0-sdhci-cd-pins-0 {
|
||||
+ marvell,pins = "mpp43";
|
||||
+ marvell,function = "sdio";
|
||||
+ };
|
||||
+ cp0_sdhci_pins: cp0-sdhi-pins-0 {
|
||||
+ marvell,pins = "mpp56", "mpp57", "mpp58",
|
||||
+ "mpp59", "mpp60", "mpp61";
|
||||
+ marvell,function = "sdio";
|
||||
+ };
|
||||
+ cp0_spi1_pins: cp0-spi-pins-1 {
|
||||
+ marvell,pins = "mpp12", "mpp13", "mpp14", "mpp15", "mpp16";
|
||||
+ marvell,function = "spi1";
|
||||
+ };
|
||||
+ };
|
||||
+};
|
||||
diff --git a/target/linux/mvebu/image/cortexa72.mk b/target/linux/mvebu/image/cortexa72.mk
|
||||
index c4fb76f4f5..e342014e1a 100644
|
||||
--- a/target/linux/mvebu/image/cortexa72.mk
|
||||
+++ b/target/linux/mvebu/image/cortexa72.mk
|
||||
@@ -68,6 +68,16 @@ define Device/iei_puzzle-m902
|
||||
endef
|
||||
TARGET_DEVICES += iei_puzzle-m902
|
||||
|
||||
+define Device/solidrun_cn9130-cf-base
|
||||
+ $(call Device/Default-arm64)
|
||||
+ DEVICE_VENDOR := SolidRun
|
||||
+ DEVICE_MODEL := ClearFog
|
||||
+ DEVICE_VARIANT := CN9130-Base
|
||||
+ DEVICE_DTS := cn9130-cf-base
|
||||
+ SUPPORTED_DEVICES := solidrun,cn9130-cf-base
|
||||
+endef
|
||||
+TARGET_DEVICES += solidrun_cn9130-cf-base
|
||||
+
|
||||
define Device/solidrun_cn9130-cf-pro
|
||||
$(call Device/Default-arm64)
|
||||
DEVICE_VENDOR := SolidRun
|
||||
--
|
||||
2.42.0
|
||||
|
||||
|
|
@ -0,0 +1,6 @@
|
|||
WANDEV=switch0
|
||||
SWITCHDEV=switch0
|
||||
CLIENT_PORTS="eth0 eth1"
|
||||
WAN_PORTS="eth2"
|
||||
DSA=1
|
||||
ROUTERMAC=$(cat /sys/class/net/eth2/address)
|
||||
|
|
@ -16,6 +16,7 @@ get_cpu_port() {
|
|||
CPUPORT="6t"
|
||||
;;
|
||||
netgear,r6220|\
|
||||
solidrun,cn9130-cf-base|\
|
||||
solidrun,cn9130-cf-pro|\
|
||||
tplink,cpe210-v2|\
|
||||
tplink,cpe210-v3|\
|
||||
|
|
|
|||
Loading…
Reference in New Issue