openwrt/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4019-gl-b2200.dts

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// SPDX-License-Identifier: GPL-2.0-only OR MIT
#include "qcom-ipq4019.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/soc/qcom,tcsr.h>
/ {
model = "GL.iNet GL-B2200";
compatible = "glinet,gl-b2200", "qcom,ipq4019";
memory {
device_type = "memory";
reg = <0x80000000 0x10000000>;
};
chosen {
bootargs-append = " root=/dev/mmcblk0p2 rw rootwait clk_ignore_unused";
};
soc {
rng@22000 {
status = "okay";
};
mdio@90000 {
status = "okay";
};
ess-psgmii@98000 {
status = "okay";
};
tcsr@1949000 {
compatible = "qcom,tcsr";
reg = <0x1949000 0x100>;
qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
};
tcsr@194b000 {
/* select hostmode */
compatible = "qcom,tcsr";
reg = <0x194b000 0x100>;
qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
status = "okay";
};
ess_tcsr@1953000 {
compatible = "qcom,tcsr";
reg = <0x1953000 0x1000>;
qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
};
tcsr@1957000 {
compatible = "qcom,tcsr";
reg = <0x1957000 0x100>;
qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
};
crypto@8e3a000 {
status = "okay";
};
ess-switch@c000000 {
status = "okay";
switch_lan_bmp = <0x2e>;
switch_wan_bmp = <0x10>;
};
edma@c080000 {
status = "okay";
};
};
keys {
compatible = "gpio-keys";
wps {
label = "wps";
gpios = <&tlmm 18 GPIO_ACTIVE_LOW>;
linux,code = <KEY_WPS_BUTTON>;
linux,input-type = <1>;
};
reset {
label = "reset";
gpios = <&tlmm 43 GPIO_ACTIVE_LOW>;
linux,code = <KEY_RESTART>;
linux,input-type = <1>;
};
};
leds {
compatible = "gpio-leds";
power_blue {
label = "blue:power";
gpios = <&tlmm 57 GPIO_ACTIVE_HIGH>;
default-state = "on";
};
internet_blue {
label = "blue:internet";
gpios = <&tlmm 60 GPIO_ACTIVE_HIGH>;
};
power_white {
label = "white:power";
gpios = <&tlmm 61 GPIO_ACTIVE_LOW>;
};
internet_white {
label = "white:internet";
gpios = <&tlmm 66 GPIO_ACTIVE_LOW>;
};
};
};
&gmac1 {
qcom,phy_mdio_addr = <3>;
qcom,poll_required = <1>;
qcom,forced_speed = <1000>;
qcom,forced_duplex = <1>;
vlan_tag = <2 0x10>;
};
&gmac0 {
vlan_tag = <1 0x2e>;
};
&vqmmc {
status = "okay";
};
&sdhci {
status = "okay";
pinctrl-0 = <&sd_pins>;
pinctrl-names = "default";
cd-gpios = <&tlmm 3 GPIO_ACTIVE_LOW>;
vqmmc-supply = <&vqmmc>;
};
&blsp_dma {
status = "okay";
};
&cryptobam {
status = "okay";
};
&blsp1_spi1 {
pinctrl-0 = <&spi_0_pins>;
pinctrl-names = "default";
status = "okay";
cs-gpios = <&tlmm 12 GPIO_ACTIVE_HIGH>;
flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <24000000>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "SBL1";
reg = <0x0 0x40000>;
read-only;
};
partition@40000 {
label = "MIBIB";
reg = <0x40000 0x20000>;
read-only;
};
partition@60000 {
label = "QSEE";
reg = <0x60000 0x60000>;
read-only;
};
partition@c0000 {
label = "CDT";
reg = <0xc0000 0x10000>;
read-only;
};
partition@d0000 {
label = "DDRPARAMS";
reg = <0xd0000 0x10000>;
read-only;
};
partition@e0000 {
label = "APPSBLENV";
reg = <0xe0000 0x10000>;
read-only;
};
partition@f0000 {
label = "APPSBL";
reg = <0xf0000 0x80000>;
read-only;
};
partition@170000 {
label = "ART";
reg = <0x170000 0x10000>;
read-only;
};
};
};
};
&blsp1_spi2 {
pinctrl-0 = <&spi_1_pins>;
pinctrl-names = "default";
status = "okay";
spidev1: spi@0 {
compatible = "siliconlabs,si3210";
reg = <0>;
spi-max-frequency = <24000000>;
};
};
&blsp1_uart1 {
pinctrl-0 = <&serial_pins>;
pinctrl-names = "default";
status = "okay";
};
&blsp1_uart2 {
pinctrl-0 = <&serial_1_pins>;
pinctrl-names = "default";
status = "okay";
};
&tlmm {
serial_pins: serial_pinmux {
mux {
pins = "gpio16", "gpio17";
function = "blsp_uart0";
bias-disable;
};
};
serial_1_pins: serial1_pinmux {
mux {
pins = "gpio8", "gpio9",
"gpio10", "gpio11";
function = "blsp_uart1";
bias-disable;
};
};
spi_0_pins: spi_0_pinmux {
pinmux {
function = "blsp_spi0";
pins = "gpio13", "gpio14", "gpio15";
};
pinmux_cs {
function = "gpio";
pins = "gpio12";
};
pinconf {
pins = "gpio13", "gpio14", "gpio15";
drive-strength = <12>;
bias-disable;
};
pinconf_cs {
pins = "gpio12";
drive-strength = <2>;
bias-disable;
output-high;
};
};
spi_1_pins: spi_1_pinmux {
mux {
pins = "gpio44", "gpio46", "gpio47";
function = "blsp_spi1";
bias-disable;
};
cs {
pins = "gpio45";
function = "gpio";
bias-pull-up;
};
reset {
pins = "gpio43";
function = "gpio";
output-high;
};
mux_2 {
pins = "gpio35";
function = "gpio";
output-high;
};
host_int {
pins = "gpio2";
function = "gpio";
input;
};
wake {
pins = "gpio48";
function = "gpio";
output-high;
};
};
sd_pins: sd_pins {
pinmux {
function = "sdio";
pins = "gpio23", "gpio24", "gpio25", "gpio26",
"gpio29", "gpio30", "gpio31", "gpio32";
drive-strength = <10>;
};
pinmux_sd_clk {
function = "sdio";
pins = "gpio27";
drive-strength = <16>;
};
pinmux_sd7 {
function = "sdio";
pins = "gpio28";
drive-strength = <10>;
bias-disable;
};
};
};
&pcie0 {
status = "okay";
perst-gpio = <&tlmm 38 GPIO_ACTIVE_LOW>;
wake-gpio = <&tlmm 50 GPIO_ACTIVE_LOW>;
bridge@0,0 {
reg = <0x00000000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
ranges;
wifi2: wifi@1,0 {
status = "okay";
compatible = "qcom,ath10k";
reg = <0x00010000 0 0 0 0>;
qcom,ath10k-calibration-variant = "GL-B2200";
};
};
};
&wifi0 {
status = "okay";
qcom,ath10k-calibration-variant = "GL-B2200";
};
&wifi1 {
status = "okay";
qcom,ath10k-calibration-variant = "GL-B2200";
};