1
0
mirror of https://git.openwrt.org/openwrt/openwrt.git synced 2024-06-13 18:53:52 +02:00
openwrt/target/linux/mediatek/patches-5.10/173-arm-dts-mt7623-add-musb-device-nodes.patch
John Audia 6b1cd3e345 kernel: bump 5.10 to 5.10.61
Manually rebased:
  bcm27xx/patches-5.10/950-1031-net-lan78xx-Ack-pending-PHY-ints-when-resetting.patch

Removed upstreamed:
  mvebu/patches-5.10/101-cpufreq-armada-37xx-forbid-cpufreq-for-1.2-GHz-variant.patch

All other patches automatically rebased.

Build system: x86_64
Build-tested: bcm2711/RPi4B
Run-tested: bcm2711/RPi4B

No dmesg regressions, everything functional

Signed-off-by: John Audia <graysky@archlinux.us>
2021-08-29 16:30:20 +02:00

70 lines
1.8 KiB
Diff

From 21d106f15262f5a2ef7531636e0703ee61c33c61 Mon Sep 17 00:00:00 2001
From: Sungbo Eo <mans0n@gorani.run>
Date: Sun, 8 Aug 2021 21:38:40 +0900
Subject: [PATCH 2/2] arm: dts: mt7623: add musb device nodes
MT7623 has an musb controller that is compatible with the one from MT2701.
Signed-off-by: Sungbo Eo <mans0n@gorani.run>
---
arch/arm/boot/dts/mt7623.dtsi | 34 ++++++++++++++++++++++++++++++++++
arch/arm/boot/dts/mt7623a.dtsi | 4 ++++
2 files changed, 38 insertions(+)
--- a/arch/arm/boot/dts/mt7623.dtsi
+++ b/arch/arm/boot/dts/mt7623.dtsi
@@ -585,6 +585,40 @@
status = "disabled";
};
+ usb0: usb@11200000 {
+ compatible = "mediatek,mt7623-musb",
+ "mediatek,mtk-musb";
+ reg = <0 0x11200000 0 0x1000>;
+ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-names = "mc";
+ phys = <&u2port2 PHY_TYPE_USB2>;
+ dr_mode = "otg";
+ clocks = <&pericfg CLK_PERI_USB0>,
+ <&pericfg CLK_PERI_USB0_MCU>,
+ <&pericfg CLK_PERI_USB_SLV>;
+ clock-names = "main","mcu","univpll";
+ power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>;
+ status = "disabled";
+ };
+
+ u2phy1: t-phy@11210000 {
+ compatible = "mediatek,mt7623-tphy",
+ "mediatek,generic-tphy-v1";
+ reg = <0 0x11210000 0 0x0800>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ status = "disabled";
+
+ u2port2: usb-phy@11210800 {
+ reg = <0 0x11210800 0 0x0100>;
+ clocks = <&topckgen CLK_TOP_USB_PHY48M>;
+ clock-names = "ref";
+ #phy-cells = <1>;
+ status = "okay";
+ };
+ };
+
audsys: clock-controller@11220000 {
compatible = "mediatek,mt7623-audsys",
"mediatek,mt2701-audsys",
--- a/arch/arm/boot/dts/mt7623a.dtsi
+++ b/arch/arm/boot/dts/mt7623a.dtsi
@@ -35,6 +35,10 @@
clock-names = "ethif";
};
+&usb0 {
+ power-domains = <&scpsys MT7623A_POWER_DOMAIN_IFR_MSC>;
+};
+
&usb1 {
power-domains = <&scpsys MT7623A_POWER_DOMAIN_HIF>;
};