131 lines
4.3 KiB
Diff
131 lines
4.3 KiB
Diff
From e19de30d20809af3221ef8a2648b8a8a52e02d90 Mon Sep 17 00:00:00 2001
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From: Daniel Golle <daniel@makrotopia.org>
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Date: Wed, 21 Sep 2022 01:23:14 +0100
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Subject: [PATCH 1/1] net: dsa: mt7530: add support for in-band link status
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Read link status from SGMII PCS for in-band managed 2500Base-X and
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1000Base-X connection on a MAC port of the MT7531. This is needed to
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get the SFP cage working which is connected to SGMII interface of
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port 5 of the MT7531 switch IC on the Bananapi BPi-R3 board.
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While at it also handle an_complete for both the autoneg and the
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non-autoneg codepath.
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Signed-off-by: Daniel Golle <daniel@makrotopia.org>
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Signed-off-by: David S. Miller <davem@davemloft.net>
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---
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drivers/net/dsa/mt7530.c | 50 +++++++++++++++++++++++++++++-----------
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drivers/net/dsa/mt7530.h | 1 +
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2 files changed, 38 insertions(+), 13 deletions(-)
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--- a/drivers/net/dsa/mt7530.c
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+++ b/drivers/net/dsa/mt7530.c
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@@ -2721,9 +2721,6 @@ mt7531_mac_config(struct dsa_switch *ds,
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case PHY_INTERFACE_MODE_NA:
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case PHY_INTERFACE_MODE_1000BASEX:
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case PHY_INTERFACE_MODE_2500BASEX:
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- if (phylink_autoneg_inband(mode))
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- return -EINVAL;
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-
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return mt7531_sgmii_setup_mode_force(priv, port, interface);
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default:
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return -EINVAL;
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@@ -2799,13 +2796,6 @@ unsupported:
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return;
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}
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- if (phylink_autoneg_inband(mode) &&
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- state->interface != PHY_INTERFACE_MODE_SGMII) {
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- dev_err(ds->dev, "%s: in-band negotiation unsupported\n",
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- __func__);
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- return;
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- }
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-
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mcr_cur = mt7530_read(priv, MT7530_PMCR_P(port));
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mcr_new = mcr_cur;
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mcr_new &= ~PMCR_LINK_SETTINGS_MASK;
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@@ -2942,6 +2932,9 @@ static void mt753x_phylink_get_caps(stru
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config->mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE |
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MAC_10 | MAC_100 | MAC_1000FD;
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+ if ((priv->id == ID_MT7531) && mt753x_is_mac_port(port))
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+ config->mac_capabilities |= MAC_2500FD;
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+
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/* This driver does not make use of the speed, duplex, pause or the
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* advertisement in its mac_config, so it is safe to mark this driver
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* as non-legacy.
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@@ -3007,6 +3000,7 @@ mt7531_sgmii_pcs_get_state_an(struct mt7
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status = mt7530_read(priv, MT7531_PCS_CONTROL_1(port));
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state->link = !!(status & MT7531_SGMII_LINK_STATUS);
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+ state->an_complete = !!(status & MT7531_SGMII_AN_COMPLETE);
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if (state->interface == PHY_INTERFACE_MODE_SGMII &&
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(status & MT7531_SGMII_AN_ENABLE)) {
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val = mt7530_read(priv, MT7531_PCS_SPEED_ABILITY(port));
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@@ -3037,16 +3031,44 @@ mt7531_sgmii_pcs_get_state_an(struct mt7
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return 0;
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}
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+static void
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+mt7531_sgmii_pcs_get_state_inband(struct mt7530_priv *priv, int port,
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+ struct phylink_link_state *state)
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+{
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+ unsigned int val;
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+
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+ val = mt7530_read(priv, MT7531_PCS_CONTROL_1(port));
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+ state->link = !!(val & MT7531_SGMII_LINK_STATUS);
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+ if (!state->link)
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+ return;
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+
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+ state->an_complete = state->link;
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+
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+ if (state->interface == PHY_INTERFACE_MODE_2500BASEX)
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+ state->speed = SPEED_2500;
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+ else
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+ state->speed = SPEED_1000;
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+
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+ state->duplex = DUPLEX_FULL;
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+ state->pause = MLO_PAUSE_NONE;
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+}
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+
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static void mt7531_pcs_get_state(struct phylink_pcs *pcs,
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struct phylink_link_state *state)
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{
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struct mt7530_priv *priv = pcs_to_mt753x_pcs(pcs)->priv;
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int port = pcs_to_mt753x_pcs(pcs)->port;
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- if (state->interface == PHY_INTERFACE_MODE_SGMII)
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+ if (state->interface == PHY_INTERFACE_MODE_SGMII) {
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mt7531_sgmii_pcs_get_state_an(priv, port, state);
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- else
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- state->link = false;
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+ return;
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+ } else if ((state->interface == PHY_INTERFACE_MODE_1000BASEX) ||
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+ (state->interface == PHY_INTERFACE_MODE_2500BASEX)) {
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+ mt7531_sgmii_pcs_get_state_inband(priv, port, state);
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+ return;
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+ }
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+
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+ state->link = false;
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}
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static int mt753x_pcs_config(struct phylink_pcs *pcs, unsigned int mode,
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@@ -3087,6 +3109,8 @@ mt753x_setup(struct dsa_switch *ds)
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priv->pcs[i].pcs.ops = priv->info->pcs_ops;
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priv->pcs[i].priv = priv;
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priv->pcs[i].port = i;
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+ if (mt753x_is_mac_port(i))
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+ priv->pcs[i].pcs.poll = 1;
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}
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ret = priv->info->sw_setup(ds);
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--- a/drivers/net/dsa/mt7530.h
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+++ b/drivers/net/dsa/mt7530.h
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@@ -373,6 +373,7 @@ enum mt7530_vlan_port_acc_frm {
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#define MT7531_SGMII_LINK_STATUS BIT(18)
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#define MT7531_SGMII_AN_ENABLE BIT(12)
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#define MT7531_SGMII_AN_RESTART BIT(9)
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+#define MT7531_SGMII_AN_COMPLETE BIT(21)
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/* Register for SGMII PCS_SPPED_ABILITY */
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#define MT7531_PCS_SPEED_ABILITY(p) MT7531_SGMII_REG(p, 0x08)
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