131 lines
4.5 KiB
Diff
131 lines
4.5 KiB
Diff
From 0d2351dc2768061689abd4de1529fa206bbd574e Mon Sep 17 00:00:00 2001
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From: "Russell King (Oracle)" <rmk+kernel@armlinux.org.uk>
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Date: Thu, 27 Oct 2022 14:10:58 +0100
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Subject: [PATCH 04/10] net: mtk_eth_soc: convert mtk_sgmii to use
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regmap_update_bits()
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mtk_sgmii does a lot of read-modify-write operations, for which there
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is a specific regmap function. Use this function instead of open-coding
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the operations.
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Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
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Signed-off-by: Jakub Kicinski <kuba@kernel.org>
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---
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drivers/net/ethernet/mediatek/mtk_sgmii.c | 61 ++++++++++-------------
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1 file changed, 26 insertions(+), 35 deletions(-)
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--- a/drivers/net/ethernet/mediatek/mtk_sgmii.c
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+++ b/drivers/net/ethernet/mediatek/mtk_sgmii.c
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@@ -36,23 +36,18 @@ static void mtk_pcs_get_state(struct phy
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/* For SGMII interface mode */
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static void mtk_pcs_setup_mode_an(struct mtk_pcs *mpcs)
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{
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- unsigned int val;
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-
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/* Setup the link timer and QPHY power up inside SGMIISYS */
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regmap_write(mpcs->regmap, SGMSYS_PCS_LINK_TIMER,
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SGMII_LINK_TIMER_DEFAULT);
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- regmap_read(mpcs->regmap, SGMSYS_SGMII_MODE, &val);
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- val |= SGMII_REMOTE_FAULT_DIS;
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- regmap_write(mpcs->regmap, SGMSYS_SGMII_MODE, val);
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-
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- regmap_read(mpcs->regmap, SGMSYS_PCS_CONTROL_1, &val);
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- val |= SGMII_AN_RESTART;
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- regmap_write(mpcs->regmap, SGMSYS_PCS_CONTROL_1, val);
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-
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- regmap_read(mpcs->regmap, SGMSYS_QPHY_PWR_STATE_CTRL, &val);
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- val &= ~SGMII_PHYA_PWD;
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- regmap_write(mpcs->regmap, SGMSYS_QPHY_PWR_STATE_CTRL, val);
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+ regmap_update_bits(mpcs->regmap, SGMSYS_SGMII_MODE,
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+ SGMII_REMOTE_FAULT_DIS, SGMII_REMOTE_FAULT_DIS);
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+
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+ regmap_update_bits(mpcs->regmap, SGMSYS_PCS_CONTROL_1,
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+ SGMII_AN_RESTART, SGMII_AN_RESTART);
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+
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+ regmap_update_bits(mpcs->regmap, SGMSYS_QPHY_PWR_STATE_CTRL,
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+ SGMII_PHYA_PWD, 0);
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}
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/* For 1000BASE-X and 2500BASE-X interface modes, which operate at a
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@@ -61,29 +56,26 @@ static void mtk_pcs_setup_mode_an(struct
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static void mtk_pcs_setup_mode_force(struct mtk_pcs *mpcs,
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phy_interface_t interface)
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{
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- unsigned int val;
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+ unsigned int rgc3;
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- regmap_read(mpcs->regmap, mpcs->ana_rgc3, &val);
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- val &= ~RG_PHY_SPEED_MASK;
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if (interface == PHY_INTERFACE_MODE_2500BASEX)
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- val |= RG_PHY_SPEED_3_125G;
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- regmap_write(mpcs->regmap, mpcs->ana_rgc3, val);
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+ rgc3 = RG_PHY_SPEED_3_125G;
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+
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+ regmap_update_bits(mpcs->regmap, mpcs->ana_rgc3,
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+ RG_PHY_SPEED_3_125G, rgc3);
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/* Disable SGMII AN */
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- regmap_read(mpcs->regmap, SGMSYS_PCS_CONTROL_1, &val);
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- val &= ~SGMII_AN_ENABLE;
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- regmap_write(mpcs->regmap, SGMSYS_PCS_CONTROL_1, val);
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+ regmap_update_bits(mpcs->regmap, SGMSYS_PCS_CONTROL_1,
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+ SGMII_AN_ENABLE, 0);
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/* Set the speed etc but leave the duplex unchanged */
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- regmap_read(mpcs->regmap, SGMSYS_SGMII_MODE, &val);
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- val &= SGMII_DUPLEX_FULL | ~SGMII_IF_MODE_MASK;
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- val |= SGMII_SPEED_1000;
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- regmap_write(mpcs->regmap, SGMSYS_SGMII_MODE, val);
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+ regmap_update_bits(mpcs->regmap, SGMSYS_SGMII_MODE,
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+ SGMII_IF_MODE_MASK & ~SGMII_DUPLEX_FULL,
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+ SGMII_SPEED_1000);
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/* Release PHYA power down state */
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- regmap_read(mpcs->regmap, SGMSYS_QPHY_PWR_STATE_CTRL, &val);
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- val &= ~SGMII_PHYA_PWD;
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- regmap_write(mpcs->regmap, SGMSYS_QPHY_PWR_STATE_CTRL, val);
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+ regmap_update_bits(mpcs->regmap, SGMSYS_QPHY_PWR_STATE_CTRL,
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+ SGMII_PHYA_PWD, 0);
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}
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static int mtk_pcs_config(struct phylink_pcs *pcs, unsigned int mode,
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@@ -105,29 +97,28 @@ static int mtk_pcs_config(struct phylink
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static void mtk_pcs_restart_an(struct phylink_pcs *pcs)
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{
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struct mtk_pcs *mpcs = pcs_to_mtk_pcs(pcs);
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- unsigned int val;
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- regmap_read(mpcs->regmap, SGMSYS_PCS_CONTROL_1, &val);
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- val |= SGMII_AN_RESTART;
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- regmap_write(mpcs->regmap, SGMSYS_PCS_CONTROL_1, val);
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+ regmap_update_bits(mpcs->regmap, SGMSYS_PCS_CONTROL_1,
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+ SGMII_AN_RESTART, SGMII_AN_RESTART);
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}
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static void mtk_pcs_link_up(struct phylink_pcs *pcs, unsigned int mode,
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phy_interface_t interface, int speed, int duplex)
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{
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struct mtk_pcs *mpcs = pcs_to_mtk_pcs(pcs);
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- unsigned int val;
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+ unsigned int sgm_mode;
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if (!phy_interface_mode_is_8023z(interface))
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return;
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/* SGMII force duplex setting */
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- regmap_read(mpcs->regmap, SGMSYS_SGMII_MODE, &val);
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- val &= ~SGMII_DUPLEX_FULL;
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if (duplex == DUPLEX_FULL)
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- val |= SGMII_DUPLEX_FULL;
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+ sgm_mode = SGMII_DUPLEX_FULL;
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+ else
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+ sgm_mode = 0;
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- regmap_write(mpcs->regmap, SGMSYS_SGMII_MODE, val);
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+ regmap_update_bits(mpcs->regmap, SGMSYS_SGMII_MODE,
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+ SGMII_DUPLEX_FULL, sgm_mode);
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}
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static const struct phylink_pcs_ops mtk_pcs_ops = {
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