139 lines
4.0 KiB
Diff
139 lines
4.0 KiB
Diff
From: Lorenzo Bianconi <lorenzo@kernel.org>
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Date: Fri, 20 May 2022 20:11:39 +0200
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Subject: [PATCH] net: ethernet: mtk_eth_soc: introduce support for mt7986
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chipset
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Add support for mt7986-eth driver available on mt7986 soc.
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Tested-by: Sam Shih <sam.shih@mediatek.com>
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Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
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Signed-off-by: David S. Miller <davem@davemloft.net>
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---
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--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
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+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
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@@ -87,6 +87,43 @@ static const struct mtk_reg_map mt7628_r
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},
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};
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+static const struct mtk_reg_map mt7986_reg_map = {
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+ .tx_irq_mask = 0x461c,
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+ .tx_irq_status = 0x4618,
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+ .pdma = {
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+ .rx_ptr = 0x6100,
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+ .rx_cnt_cfg = 0x6104,
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+ .pcrx_ptr = 0x6108,
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+ .glo_cfg = 0x6204,
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+ .rst_idx = 0x6208,
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+ .delay_irq = 0x620c,
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+ .irq_status = 0x6220,
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+ .irq_mask = 0x6228,
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+ .int_grp = 0x6250,
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+ },
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+ .qdma = {
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+ .qtx_cfg = 0x4400,
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+ .rx_ptr = 0x4500,
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+ .rx_cnt_cfg = 0x4504,
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+ .qcrx_ptr = 0x4508,
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+ .glo_cfg = 0x4604,
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+ .rst_idx = 0x4608,
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+ .delay_irq = 0x460c,
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+ .fc_th = 0x4610,
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+ .int_grp = 0x4620,
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+ .hred = 0x4644,
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+ .ctx_ptr = 0x4700,
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+ .dtx_ptr = 0x4704,
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+ .crx_ptr = 0x4710,
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+ .drx_ptr = 0x4714,
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+ .fq_head = 0x4720,
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+ .fq_tail = 0x4724,
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+ .fq_count = 0x4728,
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+ .fq_blen = 0x472c,
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+ },
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+ .gdm1_cnt = 0x1c00,
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+};
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+
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/* strings used by ethtool */
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static const struct mtk_ethtool_stats {
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char str[ETH_GSTRING_LEN];
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@@ -110,7 +147,7 @@ static const char * const mtk_clks_sourc
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"ethif", "sgmiitop", "esw", "gp0", "gp1", "gp2", "fe", "trgpll",
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"sgmii_tx250m", "sgmii_rx250m", "sgmii_cdr_ref", "sgmii_cdr_fb",
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"sgmii2_tx250m", "sgmii2_rx250m", "sgmii2_cdr_ref", "sgmii2_cdr_fb",
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- "sgmii_ck", "eth2pll",
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+ "sgmii_ck", "eth2pll", "wocpu0", "wocpu1", "netsys0", "netsys1"
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};
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void mtk_w32(struct mtk_eth *eth, u32 val, unsigned reg)
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@@ -3712,6 +3749,21 @@ static const struct mtk_soc_data mt7629_
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},
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};
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+static const struct mtk_soc_data mt7986_data = {
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+ .reg_map = &mt7986_reg_map,
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+ .ana_rgc3 = 0x128,
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+ .caps = MT7986_CAPS,
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+ .required_clks = MT7986_CLKS_BITMAP,
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+ .required_pctl = false,
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+ .txrx = {
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+ .txd_size = sizeof(struct mtk_tx_dma_v2),
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+ .rxd_size = sizeof(struct mtk_rx_dma_v2),
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+ .rx_irq_done_mask = MTK_RX_DONE_INT_V2,
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+ .dma_max_len = MTK_TX_DMA_BUF_LEN_V2,
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+ .dma_len_offset = 8,
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+ },
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+};
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+
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static const struct mtk_soc_data rt5350_data = {
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.reg_map = &mt7628_reg_map,
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.caps = MT7628_CAPS,
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@@ -3734,6 +3786,7 @@ const struct of_device_id of_mtk_match[]
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{ .compatible = "mediatek,mt7622-eth", .data = &mt7622_data},
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{ .compatible = "mediatek,mt7623-eth", .data = &mt7623_data},
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{ .compatible = "mediatek,mt7629-eth", .data = &mt7629_data},
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+ { .compatible = "mediatek,mt7986-eth", .data = &mt7986_data},
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{ .compatible = "ralink,rt5350-eth", .data = &rt5350_data},
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{},
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};
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--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
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+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
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@@ -624,6 +624,10 @@ enum mtk_clks_map {
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MTK_CLK_SGMII2_CDR_FB,
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MTK_CLK_SGMII_CK,
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MTK_CLK_ETH2PLL,
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+ MTK_CLK_WOCPU0,
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+ MTK_CLK_WOCPU1,
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+ MTK_CLK_NETSYS0,
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+ MTK_CLK_NETSYS1,
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MTK_CLK_MAX
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};
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@@ -654,6 +658,16 @@ enum mtk_clks_map {
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BIT(MTK_CLK_SGMII2_CDR_FB) | \
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BIT(MTK_CLK_SGMII_CK) | \
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BIT(MTK_CLK_ETH2PLL) | BIT(MTK_CLK_SGMIITOP))
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+#define MT7986_CLKS_BITMAP (BIT(MTK_CLK_FE) | BIT(MTK_CLK_GP2) | BIT(MTK_CLK_GP1) | \
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+ BIT(MTK_CLK_WOCPU1) | BIT(MTK_CLK_WOCPU0) | \
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+ BIT(MTK_CLK_SGMII_TX_250M) | \
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+ BIT(MTK_CLK_SGMII_RX_250M) | \
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+ BIT(MTK_CLK_SGMII_CDR_REF) | \
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+ BIT(MTK_CLK_SGMII_CDR_FB) | \
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+ BIT(MTK_CLK_SGMII2_TX_250M) | \
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+ BIT(MTK_CLK_SGMII2_RX_250M) | \
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+ BIT(MTK_CLK_SGMII2_CDR_REF) | \
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+ BIT(MTK_CLK_SGMII2_CDR_FB))
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enum mtk_dev_state {
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MTK_HW_INIT,
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@@ -852,6 +866,10 @@ enum mkt_eth_capabilities {
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MTK_MUX_U3_GMAC2_TO_QPHY | \
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MTK_MUX_GMAC12_TO_GEPHY_SGMII | MTK_QDMA)
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+#define MT7986_CAPS (MTK_GMAC1_SGMII | MTK_GMAC2_SGMII | \
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+ MTK_MUX_GMAC12_TO_GEPHY_SGMII | MTK_QDMA | \
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+ MTK_NETSYS_V2 | MTK_RSTCTRL_PPE1)
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+
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struct mtk_tx_dma_desc_info {
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dma_addr_t addr;
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u32 size;
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