146 lines
4.7 KiB
Diff
146 lines
4.7 KiB
Diff
--- a/drivers/irqchip/irq-realtek-rtl.c
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+++ b/drivers/irqchip/irq-realtek-rtl.c
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@@ -28,6 +28,7 @@ static DEFINE_RAW_SPINLOCK(irq_lock);
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#define REG(offset, cpu) (realtek_ictl_base[cpu] + offset)
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+static u32 realtek_ictl_unmask[NR_CPUS];
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static void __iomem *realtek_ictl_base[NR_CPUS];
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static cpumask_t realtek_ictl_cpu_configurable;
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@@ -41,11 +42,29 @@ struct realtek_ictl_output {
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};
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/*
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- * IRR0-IRR3 store 4 bits per interrupt, but Realtek uses inverted numbering,
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- * placing IRQ 31 in the first four bits. A routing value of '0' means the
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- * interrupt is left disconnected. Routing values {1..15} connect to output
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- * lines {0..14}.
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+ * Per CPU we have a set of 5 registers that determine interrupt handling for
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+ * 32 external interrupts. GIMR (enable/disable interrupt) plus IRR0-IRR3 that
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+ * contain "routing" or "priority" values. GIMR uses one bit for each interrupt
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+ * and IRRx store 4 bits per interrupt. Realtek uses inverted numbering,
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+ * placing IRQ 31 in the first four bits. The register combinations give the
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+ * following results for a single interrupt in the wild:
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+ *
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+ * a) GIMR = 0 / IRRx > 0 -> no interrupts
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+ * b) GIMR = 0 / IRRx = 0 -> no interrupts
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+ * c) GIMR = 1 / IRRx > 0 -> interrupts
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+ * d) GIMR = 1 / IRRx = 0 -> rare interrupts in SMP environment
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+ *
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+ * Combination d) seems to trigger interrupts only on a VPE if the other VPE
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+ * has GIMR = 0 and IRRx > 0. E.g. busy without interrupts allowed. To provide
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+ * IRQ balancing features in SMP this driver will handle the registers as
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+ * follows:
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+ *
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+ * 1) set IRRx > 0 for VPE where the interrupt is desired
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+ * 2) set IRRx = 0 for VPE where the interrupt is not desired
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+ * 3) set both GIMR = 0 to mask (disabled) interrupt
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+ * 4) set GIMR = 1 to unmask (enable) interrupt but only for VPE where IRRx > 0
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*/
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+
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#define IRR_OFFSET(idx) (4 * (3 - (idx * 4) / 32))
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#define IRR_SHIFT(idx) ((idx * 4) % 32)
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@@ -65,19 +84,33 @@ static inline void write_irr(void __iome
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writel(irr, irr0 + offset);
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}
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+static inline void enable_gimr(int hwirq, int cpu)
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+{
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+ u32 value;
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+
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+ value = readl(REG(RTL_ICTL_GIMR, cpu));
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+ value |= (BIT(hwirq) & realtek_ictl_unmask[cpu]);
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+ writel(value, REG(RTL_ICTL_GIMR, cpu));
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+}
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+
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+static inline void disable_gimr(int hwirq, int cpu)
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+{
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+ u32 value;
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+
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+ value = readl(REG(RTL_ICTL_GIMR, cpu));
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+ value &= ~BIT(hwirq);
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+ writel(value, REG(RTL_ICTL_GIMR, cpu));
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+}
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+
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static void realtek_ictl_unmask_irq(struct irq_data *i)
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{
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unsigned long flags;
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- u32 value;
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int cpu;
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raw_spin_lock_irqsave(&irq_lock, flags);
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- for_each_cpu(cpu, &realtek_ictl_cpu_configurable) {
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- value = readl(REG(RTL_ICTL_GIMR, cpu));
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- value |= BIT(i->hwirq);
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- writel(value, REG(RTL_ICTL_GIMR, cpu));
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- }
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+ for_each_cpu(cpu, &realtek_ictl_cpu_configurable)
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+ enable_gimr(i->hwirq, cpu);
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raw_spin_unlock_irqrestore(&irq_lock, flags);
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}
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@@ -85,16 +118,12 @@ static void realtek_ictl_unmask_irq(stru
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static void realtek_ictl_mask_irq(struct irq_data *i)
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{
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unsigned long flags;
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- u32 value;
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int cpu;
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raw_spin_lock_irqsave(&irq_lock, flags);
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- for_each_cpu(cpu, &realtek_ictl_cpu_configurable) {
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- value = readl(REG(RTL_ICTL_GIMR, cpu));
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- value &= ~BIT(i->hwirq);
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- writel(value, REG(RTL_ICTL_GIMR, cpu));
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- }
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+ for_each_cpu(cpu, &realtek_ictl_cpu_configurable)
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+ disable_gimr(i->hwirq, cpu);
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raw_spin_unlock_irqrestore(&irq_lock, flags);
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}
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@@ -116,11 +145,17 @@ static int __maybe_unused realtek_ictl_i
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cpumask_and(&cpu_enable, &cpu_configure, dest);
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cpumask_andnot(&cpu_disable, &cpu_configure, dest);
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- for_each_cpu(cpu, &cpu_disable)
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+ for_each_cpu(cpu, &cpu_disable) {
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write_irr(REG(RTL_ICTL_IRR0, cpu), i->hwirq, 0);
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+ realtek_ictl_unmask[cpu] &= ~BIT(i->hwirq);
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+ disable_gimr(i->hwirq, cpu);
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+ }
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- for_each_cpu(cpu, &cpu_enable)
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+ for_each_cpu(cpu, &cpu_enable) {
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write_irr(REG(RTL_ICTL_IRR0, cpu), i->hwirq, output->output_index + 1);
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+ realtek_ictl_unmask[cpu] |= BIT(i->hwirq);
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+ enable_gimr(i->hwirq, cpu);
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+ }
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irq_data_update_effective_affinity(i, &cpu_enable);
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@@ -149,6 +184,7 @@ static int intc_map(struct irq_domain *d
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output->child_mask |= BIT(hw);
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write_irr(REG(RTL_ICTL_IRR0, 0), hw, output->output_index + 1);
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+ realtek_ictl_unmask[0] |= BIT(hw);
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raw_spin_unlock_irqrestore(&irq_lock, flags);
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@@ -279,9 +315,11 @@ static int __init realtek_rtl_of_init(st
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cpumask_set_cpu(cpu, &realtek_ictl_cpu_configurable);
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/* Disable all cascaded interrupts and clear routing */
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- writel(0, REG(RTL_ICTL_GIMR, cpu));
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- for (soc_irq = 0; soc_irq < RTL_ICTL_NUM_INPUTS; soc_irq++)
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+ for (soc_irq = 0; soc_irq < RTL_ICTL_NUM_INPUTS; soc_irq++) {
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write_irr(REG(RTL_ICTL_IRR0, cpu), soc_irq, 0);
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+ realtek_ictl_unmask[cpu] &= ~BIT(soc_irq);
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+ disable_gimr(soc_irq, cpu);
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+ }
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}
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}
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