103 lines
2.4 KiB
Diff
103 lines
2.4 KiB
Diff
From a20c4e8738a00087aa5d53fe5148ed484e23d229 Mon Sep 17 00:00:00 2001
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From: Robert Marko <robimarko@gmail.com>
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Date: Sat, 31 Dec 2022 13:56:26 +0100
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Subject: [PATCH] arm64: dts: qcom: ipq8074: add CPU OPP table
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Now that there is NVMEM CPUFreq support for IPQ8074, we can add the OPP
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table for SoC.
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Signed-off-by: Robert Marko <robimarko@gmail.com>
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---
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arch/arm64/boot/dts/qcom/ipq8074.dtsi | 52 +++++++++++++++++++++++++++
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1 file changed, 52 insertions(+)
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--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
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+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
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@@ -42,6 +42,7 @@
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clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
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clock-names = "cpu";
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#cooling-cells = <2>;
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+ operating-points-v2 = <&cpu_opp_table>;
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};
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CPU1: cpu@1 {
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@@ -53,6 +54,7 @@
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clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
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clock-names = "cpu";
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#cooling-cells = <2>;
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+ operating-points-v2 = <&cpu_opp_table>;
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};
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CPU2: cpu@2 {
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@@ -64,6 +66,7 @@
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clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
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clock-names = "cpu";
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#cooling-cells = <2>;
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+ operating-points-v2 = <&cpu_opp_table>;
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};
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CPU3: cpu@3 {
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@@ -75,6 +78,7 @@
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clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
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clock-names = "cpu";
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#cooling-cells = <2>;
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+ operating-points-v2 = <&cpu_opp_table>;
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};
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L2_0: l2-cache {
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@@ -83,6 +87,54 @@
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};
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};
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+ cpu_opp_table: opp-table {
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+ compatible = "operating-points-v2-kryo-cpu";
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+ nvmem-cells = <&cpr_efuse_speedbin>;
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+ opp-shared;
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+
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+ opp-1017600000 {
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+ opp-hz = /bits/ 64 <1017600000>;
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+ opp-microvolt = <1>;
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+ opp-supported-hw = <0xf>;
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+ clock-latency-ns = <200000>;
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+ };
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+
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+ opp-1382400000 {
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+ opp-hz = /bits/ 64 <1382400000>;
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+ opp-microvolt = <2>;
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+ opp-supported-hw = <0xf>;
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+ clock-latency-ns = <200000>;
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+ };
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+
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+ opp-1651200000 {
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+ opp-hz = /bits/ 64 <1651200000>;
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+ opp-microvolt = <3>;
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+ opp-supported-hw = <0x1>;
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+ clock-latency-ns = <200000>;
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+ };
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+
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+ opp-1843200000 {
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+ opp-hz = /bits/ 64 <1843200000>;
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+ opp-microvolt = <4>;
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+ opp-supported-hw = <0x1>;
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+ clock-latency-ns = <200000>;
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+ };
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+
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+ opp-1920000000 {
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+ opp-hz = /bits/ 64 <1920000000>;
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+ opp-microvolt = <5>;
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+ opp-supported-hw = <0x1>;
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+ clock-latency-ns = <200000>;
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+ };
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+
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+ opp-2208000000 {
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+ opp-hz = /bits/ 64 <2208000000>;
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+ opp-microvolt = <6>;
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+ opp-supported-hw = <0x1>;
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+ clock-latency-ns = <200000>;
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+ };
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+ };
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+
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pmu {
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compatible = "arm,cortex-a53-pmu";
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interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
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