51 lines
1.8 KiB
Diff
51 lines
1.8 KiB
Diff
From f4c7d053d7f77cd5c1a1ba7c7ce085ddba13d1d7 Mon Sep 17 00:00:00 2001
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From: Remi Pommarel <repk@triplefau.lt>
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Date: Wed, 22 May 2019 23:33:50 +0200
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Subject: [PATCH] PCI: aardvark: Wait for endpoint to be ready before training
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link
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When configuring pcie reset pin from gpio (e.g. initially set by
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u-boot) to pcie function this pin goes low for a brief moment
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asserting the PERST# signal. Thus connected device enters fundamental
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reset process and link configuration can only begin after a minimal
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100ms delay (see [1]).
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Because the pin configuration comes from the "default" pinctrl it is
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implicitly configured before the probe callback is called:
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driver_probe_device()
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really_probe()
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...
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pinctrl_bind_pins() /* Here pin goes from gpio to PCIE reset
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function and PERST# is asserted */
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...
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drv->probe()
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[1] "PCI Express Base Specification", REV. 4.0
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PCI Express, February 19 2014, 6.6.1 Conventional Reset
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Signed-off-by: Remi Pommarel <repk@triplefau.lt>
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Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
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Acked-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
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---
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drivers/pci/controller/pci-aardvark.c | 8 ++++++++
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1 file changed, 8 insertions(+)
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--- a/drivers/pci/controller/pci-aardvark.c
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+++ b/drivers/pci/controller/pci-aardvark.c
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@@ -338,6 +338,14 @@ static void advk_pcie_setup_hw(struct ad
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reg |= PIO_CTRL_ADDR_WIN_DISABLE;
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advk_writel(pcie, reg, PIO_CTRL);
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+ /*
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+ * PERST# signal could have been asserted by pinctrl subsystem before
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+ * probe() callback has been called, making the endpoint going into
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+ * fundamental reset. As required by PCI Express spec a delay for at
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+ * least 100ms after such a reset before link training is needed.
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+ */
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+ msleep(PCI_PM_D3COLD_WAIT);
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+
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/* Start link training */
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reg = advk_readl(pcie, PCIE_CORE_LINK_CTRL_STAT_REG);
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reg |= PCIE_CORE_LINK_TRAINING;
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