32 lines
1.3 KiB
Diff
32 lines
1.3 KiB
Diff
From 5bf9ff3b9fb5ecb67a1a3517b26db3a00f2a2f11 Mon Sep 17 00:00:00 2001
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From: Ansuel Smith <ansuelsmth@gmail.com>
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Date: Fri, 14 May 2021 23:00:02 +0200
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Subject: [PATCH] net: dsa: qca8k: limit port5 delay to qca8337
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Limit port5 rx delay to qca8337. This is taken from the legacy QSDK code
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that limits the rx delay on port5 to only this particular switch version,
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on other switch only the tx and rx delay for port0 are needed.
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Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
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Reviewed-by: Andrew Lunn <andrew@lunn.ch>
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Signed-off-by: David S. Miller <davem@davemloft.net>
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---
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drivers/net/dsa/qca8k.c | 6 ++++--
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1 file changed, 4 insertions(+), 2 deletions(-)
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--- a/drivers/net/dsa/qca8k.c
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+++ b/drivers/net/dsa/qca8k.c
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@@ -1003,8 +1003,10 @@ qca8k_phylink_mac_config(struct dsa_swit
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QCA8K_PORT_PAD_RGMII_EN |
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QCA8K_PORT_PAD_RGMII_TX_DELAY(QCA8K_MAX_DELAY) |
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QCA8K_PORT_PAD_RGMII_RX_DELAY(QCA8K_MAX_DELAY));
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- qca8k_write(priv, QCA8K_REG_PORT5_PAD_CTRL,
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- QCA8K_PORT_PAD_RGMII_RX_DELAY_EN);
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+ /* QCA8337 requires to set rgmii rx delay */
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+ if (priv->switch_id == QCA8K_ID_QCA8337)
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+ qca8k_write(priv, QCA8K_REG_PORT5_PAD_CTRL,
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+ QCA8K_PORT_PAD_RGMII_RX_DELAY_EN);
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break;
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case PHY_INTERFACE_MODE_SGMII:
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case PHY_INTERFACE_MODE_1000BASEX:
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