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e39414ed07
Refreshed all patches Dropped upstreamed patches: 522-PCI-aardvark-fix-logic-in-PCI-configuration-read-write-functions.patch 523-PCI-aardvark-set-PIO_ADDR_LS-correctly-in-advk_pcie_rd_conf.patch 525-PCI-aardvark-use-isr1-instead-of-isr0-interrupt-in-legacy-irq-mode.patch 527-PCI-aardvark-fix-PCIe-max-read-request-size-setting.patch updated patches: 524-PCI-aardvark-set-host-and-device-to-the-same-MAX-payload-size.patch 030-USB-serial-option-fix-dwm-158-3g-modem-interface.patch Added new ARM64 symbol: CONFIG_ARM64_ERRATUM_1024718 Compile-tested on: cns3xxx, imx6, mvebu (arm64), x86_64 Runtime-tested on: cns3xxx, imx6, x86_64 Signed-off-by: Koen Vandeputte <koen.vandeputte@ncentric.com>
28 lines
916 B
Diff
28 lines
916 B
Diff
From 54204ef3edbb1aa2390cabba61fe185a12cc39f0 Mon Sep 17 00:00:00 2001
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From: Felix Fietkau <nbd@nbd.name>
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Date: Tue, 6 Mar 2018 08:35:44 +0100
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Subject: [PATCH 11/27] MIPS: ath79: fix register address in
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ath79_ddr_wb_flush()
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ath79_ddr_wb_flush_base has the type void __iomem *, so register offsets
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need to be a multiple of 4.
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Cc: Alban Bedel <albeu@free.fr>
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Fixes: 24b0e3e84fbf ("MIPS: ath79: Improve the DDR controller interface")
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Signed-off-by: Felix Fietkau <nbd@nbd.name>
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---
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arch/mips/ath79/common.c | 2 +-
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1 file changed, 1 insertion(+), 1 deletion(-)
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--- a/arch/mips/ath79/common.c
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+++ b/arch/mips/ath79/common.c
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@@ -58,7 +58,7 @@ EXPORT_SYMBOL_GPL(ath79_ddr_ctrl_init);
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void ath79_ddr_wb_flush(u32 reg)
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{
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- void __iomem *flush_reg = ath79_ddr_wb_flush_base + reg;
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+ void __iomem *flush_reg = ath79_ddr_wb_flush_base + (reg * 4);
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/* Flush the DDR write buffer. */
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__raw_writel(0x1, flush_reg);
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