130 lines
4.3 KiB
Diff
130 lines
4.3 KiB
Diff
From f778553f296792f4d1e8b3552603ad6116ea3eb3 Mon Sep 17 00:00:00 2001
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From: Christian Marangi <ansuelsmth@gmail.com>
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Date: Thu, 3 Nov 2022 14:49:44 +0100
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Subject: [PATCH] clk: qcom: gcc-ipq8074: rework nss_port5/6 clock to multiple
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conf
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Rework nss_port5/6 to use the new multiple configuration implementation
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and correctly fix the clocks for these port under some corner case.
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This is particularly relevant for device that have 2.5G or 10G port
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connected to port5 or port 6 on ipq8074. As the parent are shared
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across multiple port it may be required to select the correct
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configuration to accomplish the desired clock. Without this patch such
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port doesn't work in some specific ethernet speed as the clock will be
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set to the wrong frequency as we just select the first configuration for
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the related frequency instead of selecting the best one.
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Tested-by: Robert Marko <robimarko@gmail.com> # ipq8074 Qnap QHora-301W
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Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
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---
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drivers/clk/qcom/gcc-ipq8074.c | 64 +++++++++++++++++++++++++---------
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1 file changed, 48 insertions(+), 16 deletions(-)
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--- a/drivers/clk/qcom/gcc-ipq8074.c
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+++ b/drivers/clk/qcom/gcc-ipq8074.c
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@@ -1676,13 +1676,21 @@ static struct clk_regmap_div nss_port4_t
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},
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};
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+static const struct freq_conf ftbl_nss_port5_rx_clk_src_25[] = {
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+ C(P_UNIPHY1_RX, 12.5, 0, 0),
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+ C(P_UNIPHY0_RX, 5, 0, 0),
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+};
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+
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+static const struct freq_conf ftbl_nss_port5_rx_clk_src_125[] = {
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+ C(P_UNIPHY1_RX, 2.5, 0, 0),
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+ C(P_UNIPHY0_RX, 1, 0, 0),
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+};
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+
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static const struct freq_tbl ftbl_nss_port5_rx_clk_src[] = {
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F(19200000, P_XO, 1, 0, 0),
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- F(25000000, P_UNIPHY1_RX, 12.5, 0, 0),
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- F(25000000, P_UNIPHY0_RX, 5, 0, 0),
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+ FM(25000000, ftbl_nss_port5_rx_clk_src_25),
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F(78125000, P_UNIPHY1_RX, 4, 0, 0),
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- F(125000000, P_UNIPHY1_RX, 2.5, 0, 0),
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- F(125000000, P_UNIPHY0_RX, 1, 0, 0),
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+ FM(125000000, ftbl_nss_port5_rx_clk_src_125),
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F(156250000, P_UNIPHY1_RX, 2, 0, 0),
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F(312500000, P_UNIPHY1_RX, 1, 0, 0),
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{ }
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@@ -1738,13 +1746,21 @@ static struct clk_regmap_div nss_port5_r
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},
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};
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+static struct freq_conf ftbl_nss_port5_tx_clk_src_25[] = {
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+ C(P_UNIPHY1_TX, 12.5, 0, 0),
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+ C(P_UNIPHY0_TX, 5, 0, 0),
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+};
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+
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+static struct freq_conf ftbl_nss_port5_tx_clk_src_125[] = {
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+ C(P_UNIPHY1_TX, 2.5, 0, 0),
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+ C(P_UNIPHY0_TX, 1, 0, 0),
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+};
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+
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static const struct freq_tbl ftbl_nss_port5_tx_clk_src[] = {
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F(19200000, P_XO, 1, 0, 0),
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- F(25000000, P_UNIPHY1_TX, 12.5, 0, 0),
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- F(25000000, P_UNIPHY0_TX, 5, 0, 0),
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+ FM(25000000, ftbl_nss_port5_tx_clk_src_25),
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F(78125000, P_UNIPHY1_TX, 4, 0, 0),
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- F(125000000, P_UNIPHY1_TX, 2.5, 0, 0),
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- F(125000000, P_UNIPHY0_TX, 1, 0, 0),
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+ FM(125000000, ftbl_nss_port5_tx_clk_src_125),
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F(156250000, P_UNIPHY1_TX, 2, 0, 0),
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F(312500000, P_UNIPHY1_TX, 1, 0, 0),
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{ }
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@@ -1800,13 +1816,21 @@ static struct clk_regmap_div nss_port5_t
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},
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};
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+static struct freq_conf ftbl_nss_port6_rx_clk_src_25[] = {
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+ C(P_UNIPHY2_RX, 5, 0, 0),
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+ C(P_UNIPHY2_RX, 12.5, 0, 0),
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+};
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+
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+static struct freq_conf ftbl_nss_port6_rx_clk_src_125[] = {
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+ C(P_UNIPHY2_RX, 1, 0, 0),
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+ C(P_UNIPHY2_RX, 2.5, 0, 0),
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+};
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+
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static const struct freq_tbl ftbl_nss_port6_rx_clk_src[] = {
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F(19200000, P_XO, 1, 0, 0),
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- F(25000000, P_UNIPHY2_RX, 5, 0, 0),
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- F(25000000, P_UNIPHY2_RX, 12.5, 0, 0),
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+ FM(25000000, ftbl_nss_port6_rx_clk_src_25),
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F(78125000, P_UNIPHY2_RX, 4, 0, 0),
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- F(125000000, P_UNIPHY2_RX, 1, 0, 0),
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- F(125000000, P_UNIPHY2_RX, 2.5, 0, 0),
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+ FM(125000000, ftbl_nss_port6_rx_clk_src_125),
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F(156250000, P_UNIPHY2_RX, 2, 0, 0),
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F(312500000, P_UNIPHY2_RX, 1, 0, 0),
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{ }
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@@ -1857,13 +1881,21 @@ static struct clk_regmap_div nss_port6_r
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},
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};
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+static struct freq_conf ftbl_nss_port6_tx_clk_src_25[] = {
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+ C(P_UNIPHY2_TX, 5, 0, 0),
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+ C(P_UNIPHY2_TX, 12.5, 0, 0),
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+};
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+
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+static struct freq_conf ftbl_nss_port6_tx_clk_src_125[] = {
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+ C(P_UNIPHY2_TX, 1, 0, 0),
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+ C(P_UNIPHY2_TX, 2.5, 0, 0),
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+};
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+
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static const struct freq_tbl ftbl_nss_port6_tx_clk_src[] = {
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F(19200000, P_XO, 1, 0, 0),
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- F(25000000, P_UNIPHY2_TX, 5, 0, 0),
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- F(25000000, P_UNIPHY2_TX, 12.5, 0, 0),
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+ FM(25000000, ftbl_nss_port6_tx_clk_src_25),
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F(78125000, P_UNIPHY2_TX, 4, 0, 0),
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- F(125000000, P_UNIPHY2_TX, 1, 0, 0),
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- F(125000000, P_UNIPHY2_TX, 2.5, 0, 0),
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+ FM(125000000, ftbl_nss_port6_tx_clk_src_125),
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F(156250000, P_UNIPHY2_TX, 2, 0, 0),
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F(312500000, P_UNIPHY2_TX, 1, 0, 0),
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{ }
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