98 lines
2.7 KiB
Diff
98 lines
2.7 KiB
Diff
From 193856b5fe11c50a0b6ff22457dd674c1a45fec6 Mon Sep 17 00:00:00 2001
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From: John Crispin <john@phrozen.org>
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Date: Wed, 9 Sep 2020 18:31:03 +0200
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Subject: [PATCH] ARM: dts: qcom: ipq4019: add USB devicetree nodes
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Since we now have driver for the USB PHY, and USB controller is already supported by the DWC3 driver lets add the necessary nodes to DTSI.
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Signed-off-by: John Crispin <john@phrozen.org>
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Signed-off-by: Robert Marko <robert.marko@sartura.hr>
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Cc: Luka Perkov <luka.perkov@sartura.hr>
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Reviewed-by: Vinod Koul <vkoul@kernel.org>
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---
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arch/arm/boot/dts/qcom-ipq4019.dtsi | 74 +++++++++++++++++++++++++++++
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1 file changed, 74 insertions(+)
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--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
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+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
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@@ -616,5 +616,79 @@
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reg = <4>;
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};
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};
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+
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+ usb3_ss_phy: ssphy@9a000 {
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+ compatible = "qcom,usb-ss-ipq4019-phy";
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+ #phy-cells = <0>;
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+ reg = <0x9a000 0x800>;
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+ reg-names = "phy_base";
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+ resets = <&gcc USB3_UNIPHY_PHY_ARES>;
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+ reset-names = "por_rst";
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+ status = "disabled";
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+ };
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+
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+ usb3_hs_phy: hsphy@a6000 {
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+ compatible = "qcom,usb-hs-ipq4019-phy";
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+ #phy-cells = <0>;
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+ reg = <0xa6000 0x40>;
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+ reg-names = "phy_base";
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+ resets = <&gcc USB3_HSPHY_POR_ARES>, <&gcc USB3_HSPHY_S_ARES>;
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+ reset-names = "por_rst", "srif_rst";
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+ status = "disabled";
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+ };
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+
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+ usb3: usb3@8af8800 {
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+ compatible = "qcom,dwc3";
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+ reg = <0x8af8800 0x100>;
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+ clocks = <&gcc GCC_USB3_MASTER_CLK>,
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+ <&gcc GCC_USB3_SLEEP_CLK>,
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+ <&gcc GCC_USB3_MOCK_UTMI_CLK>;
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+ clock-names = "master", "sleep", "mock_utmi";
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+ ranges;
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+ status = "disabled";
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+
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+ dwc3@8a00000 {
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+ compatible = "snps,dwc3";
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+ reg = <0x8a00000 0xf8000>;
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+ interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
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+ phys = <&usb3_hs_phy>, <&usb3_ss_phy>;
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+ phy-names = "usb2-phy", "usb3-phy";
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+ dr_mode = "host";
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+ };
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+ };
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+
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+ usb2_hs_phy: hsphy@a8000 {
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+ compatible = "qcom,usb-hs-ipq4019-phy";
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+ #phy-cells = <0>;
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+ reg = <0xa8000 0x40>;
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+ reg-names = "phy_base";
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+ resets = <&gcc USB2_HSPHY_POR_ARES>, <&gcc USB2_HSPHY_S_ARES>;
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+ reset-names = "por_rst", "srif_rst";
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+ status = "disabled";
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+ };
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+
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+ usb2: usb2@60f8800 {
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+ compatible = "qcom,dwc3";
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+ reg = <0x60f8800 0x100>;
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+ clocks = <&gcc GCC_USB2_MASTER_CLK>,
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+ <&gcc GCC_USB2_SLEEP_CLK>,
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+ <&gcc GCC_USB2_MOCK_UTMI_CLK>;
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+ clock-names = "master", "sleep", "mock_utmi";
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+ ranges;
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+ status = "disabled";
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+
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+ dwc3@6000000 {
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+ compatible = "snps,dwc3";
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+ reg = <0x6000000 0xf8000>;
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+ interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
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+ phys = <&usb2_hs_phy>;
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+ phy-names = "usb2-phy";
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+ dr_mode = "host";
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+ };
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+ };
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};
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};
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