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db7e28cb98
This is an automatically generated commit. When doing `git bisect`, consider `git bisect --skip`. Signed-off-by: Nick Hainke <vincent@systemli.org>
125 lines
4.9 KiB
Diff
125 lines
4.9 KiB
Diff
From c716562753d1e51a1c53647aa77a332f97187d15 Mon Sep 17 00:00:00 2001
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From: Claudiu Beznea <claudiu.beznea@microchip.com>
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Date: Mon, 11 Oct 2021 14:27:08 +0300
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Subject: [PATCH 237/247] clk: at91: clk-master: add register definition for
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sama7g5's master clock
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SAMA7G5 has 4 master clocks (MCK1..4) which are controlled though the
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register at offset 0x30 (relative to PMC). In the last/first phase of
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suspend/resume procedure (which is architecture specific) the parent
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of master clocks are changed (via assembly code) for more power saving
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(see file arch/arm/mach-at91/pm_suspend.S, macros at91_mckx_ps_enable
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and at91_mckx_ps_restore). Thus the macros corresponding to register
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at offset 0x30 need to be shared b/w clk-master.c and pm_suspend.S.
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commit ec03f18cc222 ("clk: at91: add register definition for sama7g5's
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master clock") introduced the proper macros but didn't adapted the
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clk-master.c as well. Thus, this commit adapt the clk-master.c to use
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the macros introduced in commit ec03f18cc222 ("clk: at91: add register
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definition for sama7g5's master clock").
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Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
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Link: https://lore.kernel.org/r/20211011112719.3951784-5-claudiu.beznea@microchip.com
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Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
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Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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---
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drivers/clk/at91/clk-master.c | 50 ++++++++++++++++-------------------
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1 file changed, 23 insertions(+), 27 deletions(-)
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--- a/drivers/clk/at91/clk-master.c
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+++ b/drivers/clk/at91/clk-master.c
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@@ -17,15 +17,7 @@
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#define MASTER_DIV_SHIFT 8
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#define MASTER_DIV_MASK 0x7
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-#define PMC_MCR 0x30
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-#define PMC_MCR_ID_MSK GENMASK(3, 0)
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-#define PMC_MCR_CMD BIT(7)
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-#define PMC_MCR_DIV GENMASK(10, 8)
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-#define PMC_MCR_CSS GENMASK(20, 16)
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#define PMC_MCR_CSS_SHIFT (16)
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-#define PMC_MCR_EN BIT(28)
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-
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-#define PMC_MCR_ID(x) ((x) & PMC_MCR_ID_MSK)
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#define MASTER_MAX_ID 4
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@@ -687,20 +679,22 @@ static void clk_sama7g5_master_set(struc
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{
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unsigned long flags;
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unsigned int val, cparent;
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- unsigned int enable = status ? PMC_MCR_EN : 0;
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+ unsigned int enable = status ? AT91_PMC_MCR_V2_EN : 0;
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spin_lock_irqsave(master->lock, flags);
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- regmap_write(master->regmap, PMC_MCR, PMC_MCR_ID(master->id));
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- regmap_read(master->regmap, PMC_MCR, &val);
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- regmap_update_bits(master->regmap, PMC_MCR,
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- enable | PMC_MCR_CSS | PMC_MCR_DIV |
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- PMC_MCR_CMD | PMC_MCR_ID_MSK,
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+ regmap_write(master->regmap, AT91_PMC_MCR_V2,
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+ AT91_PMC_MCR_V2_ID(master->id));
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+ regmap_read(master->regmap, AT91_PMC_MCR_V2, &val);
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+ regmap_update_bits(master->regmap, AT91_PMC_MCR_V2,
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+ enable | AT91_PMC_MCR_V2_CSS | AT91_PMC_MCR_V2_DIV |
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+ AT91_PMC_MCR_V2_CMD | AT91_PMC_MCR_V2_ID_MSK,
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enable | (master->parent << PMC_MCR_CSS_SHIFT) |
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(master->div << MASTER_DIV_SHIFT) |
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- PMC_MCR_CMD | PMC_MCR_ID(master->id));
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+ AT91_PMC_MCR_V2_CMD |
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+ AT91_PMC_MCR_V2_ID(master->id));
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- cparent = (val & PMC_MCR_CSS) >> PMC_MCR_CSS_SHIFT;
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+ cparent = (val & AT91_PMC_MCR_V2_CSS) >> PMC_MCR_CSS_SHIFT;
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/* Wait here only if parent is being changed. */
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while ((cparent != master->parent) && !clk_master_ready(master))
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@@ -725,10 +719,12 @@ static void clk_sama7g5_master_disable(s
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spin_lock_irqsave(master->lock, flags);
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- regmap_write(master->regmap, PMC_MCR, master->id);
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- regmap_update_bits(master->regmap, PMC_MCR,
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- PMC_MCR_EN | PMC_MCR_CMD | PMC_MCR_ID_MSK,
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- PMC_MCR_CMD | PMC_MCR_ID(master->id));
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+ regmap_write(master->regmap, AT91_PMC_MCR_V2, master->id);
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+ regmap_update_bits(master->regmap, AT91_PMC_MCR_V2,
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+ AT91_PMC_MCR_V2_EN | AT91_PMC_MCR_V2_CMD |
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+ AT91_PMC_MCR_V2_ID_MSK,
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+ AT91_PMC_MCR_V2_CMD |
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+ AT91_PMC_MCR_V2_ID(master->id));
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spin_unlock_irqrestore(master->lock, flags);
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}
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@@ -741,12 +737,12 @@ static int clk_sama7g5_master_is_enabled
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spin_lock_irqsave(master->lock, flags);
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- regmap_write(master->regmap, PMC_MCR, master->id);
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- regmap_read(master->regmap, PMC_MCR, &val);
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+ regmap_write(master->regmap, AT91_PMC_MCR_V2, master->id);
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+ regmap_read(master->regmap, AT91_PMC_MCR_V2, &val);
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spin_unlock_irqrestore(master->lock, flags);
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- return !!(val & PMC_MCR_EN);
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+ return !!(val & AT91_PMC_MCR_V2_EN);
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}
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static int clk_sama7g5_master_set_rate(struct clk_hw *hw, unsigned long rate,
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@@ -842,10 +838,10 @@ at91_clk_sama7g5_register_master(struct
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master->mux_table = mux_table;
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spin_lock_irqsave(master->lock, flags);
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- regmap_write(master->regmap, PMC_MCR, master->id);
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- regmap_read(master->regmap, PMC_MCR, &val);
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- master->parent = (val & PMC_MCR_CSS) >> PMC_MCR_CSS_SHIFT;
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- master->div = (val & PMC_MCR_DIV) >> MASTER_DIV_SHIFT;
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+ regmap_write(master->regmap, AT91_PMC_MCR_V2, master->id);
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+ regmap_read(master->regmap, AT91_PMC_MCR_V2, &val);
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+ master->parent = (val & AT91_PMC_MCR_V2_CSS) >> PMC_MCR_CSS_SHIFT;
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+ master->div = (val & AT91_PMC_MCR_V2_DIV) >> MASTER_DIV_SHIFT;
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spin_unlock_irqrestore(master->lock, flags);
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hw = &master->hw;
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