69 lines
2.3 KiB
Diff
69 lines
2.3 KiB
Diff
From d31260c2f6a5cdddb052ab7cb09560eb23ce6597 Mon Sep 17 00:00:00 2001
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From: Aleksander Jan Bajkowski <olek2@wp.pl>
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Date: Thu, 15 Apr 2021 21:28:24 +0200
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Subject: [PATCH 2/5] MIPS: lantiq: dma: reset correct number of channel
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Different SoCs have a different number of channels, e.g .:
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* amazon-se has 10 channels,
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* danube+ar9 have 20 channels,
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* vr9 has 28 channels,
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* ar10 has 24 channels.
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We can read the ID register and, depending on the reported
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number of channels, reset the appropriate number of channels.
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Signed-off-by: Aleksander Jan Bajkowski <olek2@wp.pl>
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---
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arch/mips/lantiq/xway/dma.c | 11 ++++++-----
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1 file changed, 6 insertions(+), 5 deletions(-)
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--- a/arch/mips/lantiq/xway/dma.c
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+++ b/arch/mips/lantiq/xway/dma.c
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@@ -30,6 +30,7 @@
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#define LTQ_DMA_PCTRL 0x44
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#define LTQ_DMA_IRNEN 0xf4
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+#define DMA_ID_CHNR GENMASK(26, 20) /* channel number */
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#define DMA_DESCPT BIT(3) /* descriptor complete irq */
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#define DMA_TX BIT(8) /* TX channel direction */
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#define DMA_CHAN_ON BIT(0) /* channel on / off bit */
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@@ -40,7 +41,6 @@
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#define DMA_POLL BIT(31) /* turn on channel polling */
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#define DMA_CLK_DIV4 BIT(6) /* polling clock divider */
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#define DMA_2W_BURST BIT(1) /* 2 word burst length */
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-#define DMA_MAX_CHANNEL 20 /* the soc has 20 channels */
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#define DMA_ETOP_ENDIANNESS (0xf << 8) /* endianness swap etop channels */
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#define DMA_WEIGHT (BIT(17) | BIT(16)) /* default channel wheight */
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@@ -206,7 +206,7 @@ ltq_dma_init(struct platform_device *pde
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{
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struct clk *clk;
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struct resource *res;
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- unsigned id;
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+ unsigned int id, nchannels;
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int i;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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@@ -228,17 +228,18 @@ ltq_dma_init(struct platform_device *pde
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ltq_dma_w32(0, LTQ_DMA_IRNEN);
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/* reset/configure each channel */
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- for (i = 0; i < DMA_MAX_CHANNEL; i++) {
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+ id = ltq_dma_r32(LTQ_DMA_ID);
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+ nchannels = ((id & DMA_ID_CHNR) >> 20);
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+ for (i = 0; i < nchannels; i++) {
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ltq_dma_w32(i, LTQ_DMA_CS);
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ltq_dma_w32(DMA_CHAN_RST, LTQ_DMA_CCTRL);
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ltq_dma_w32(DMA_POLL | DMA_CLK_DIV4, LTQ_DMA_CPOLL);
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ltq_dma_w32_mask(DMA_CHAN_ON, 0, LTQ_DMA_CCTRL);
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}
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- id = ltq_dma_r32(LTQ_DMA_ID);
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dev_info(&pdev->dev,
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"Init done - hw rev: %X, ports: %d, channels: %d\n",
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- id & 0x1f, (id >> 16) & 0xf, id >> 20);
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+ id & 0x1f, (id >> 16) & 0xf, nchannels);
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return 0;
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}
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