94 lines
3.0 KiB
Diff
94 lines
3.0 KiB
Diff
From af3f381a59c10f6bd49d86a5ff2325b6ebeb79e9 Mon Sep 17 00:00:00 2001
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From: popcornmix <popcornmix@gmail.com>
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Date: Mon, 27 Apr 2020 19:07:50 +0100
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Subject: [PATCH] vc4_hdmi: BCM2835 requires a fixed hsm clock for CEC
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to work
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Signed-off-by: popcornmix <popcornmix@gmail.com>
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---
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drivers/gpu/drm/vc4/vc4_hdmi.c | 32 ++++++++++++++++++++++++++------
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drivers/gpu/drm/vc4/vc4_hdmi.h | 3 +++
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2 files changed, 29 insertions(+), 6 deletions(-)
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--- a/drivers/gpu/drm/vc4/vc4_hdmi.c
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+++ b/drivers/gpu/drm/vc4/vc4_hdmi.c
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@@ -580,12 +580,7 @@ static void vc4_hdmi_encoder_enable(stru
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return;
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}
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- /*
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- * The HSM rate needs to be slightly greater than the pixel clock, with
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- * a minimum of 108MHz.
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- * Use 101% as this is what the firmware uses.
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- */
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- hsm_rate = max_t(unsigned long, 108000000, (pixel_rate / 100) * 101);
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+ hsm_rate = vc4_hdmi->variant->calc_hsm_clock(vc4_hdmi, pixel_rate);
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ret = clk_set_rate(vc4_hdmi->hsm_clock, hsm_rate);
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if (ret) {
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DRM_ERROR("Failed to set HSM clock rate: %d\n", ret);
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@@ -753,6 +748,28 @@ static u32 vc5_hdmi_get_hsm_clock(struct
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return 108000000;
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}
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+static u32 vc4_hdmi_calc_hsm_clock(struct vc4_hdmi *vc4_hdmi, unsigned long pixel_rate)
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+{
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+ /*
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+ * This is the rate that is set by the firmware. The number
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+ * needs to be a bit higher than the pixel clock rate
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+ * (generally 148.5Mhz).
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+ */
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+
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+ return 163682864;
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+}
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+
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+static u32 vc5_hdmi_calc_hsm_clock(struct vc4_hdmi *vc4_hdmi, unsigned long pixel_rate)
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+{
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+ /*
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+ * The HSM rate needs to be slightly greater than the pixel clock, with
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+ * a minimum of 108MHz.
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+ * Use 101% as this is what the firmware uses.
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+ */
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+
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+ return max_t(unsigned long, 108000000, (pixel_rate / 100) * 101);
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+}
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+
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static u32 vc4_hdmi_channel_map(struct vc4_hdmi *vc4_hdmi, u32 channel_mask)
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{
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int i;
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@@ -1749,6 +1766,7 @@ static const struct vc4_hdmi_variant bcm
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.phy_rng_enable = vc4_hdmi_phy_rng_enable,
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.phy_rng_disable = vc4_hdmi_phy_rng_disable,
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.get_hsm_clock = vc4_hdmi_get_hsm_clock,
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+ .calc_hsm_clock = vc4_hdmi_calc_hsm_clock,
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.channel_map = vc4_hdmi_channel_map,
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};
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@@ -1773,6 +1791,7 @@ static const struct vc4_hdmi_variant bcm
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.phy_rng_enable = vc5_hdmi_phy_rng_enable,
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.phy_rng_disable = vc5_hdmi_phy_rng_disable,
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.get_hsm_clock = vc5_hdmi_get_hsm_clock,
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+ .calc_hsm_clock = vc5_hdmi_calc_hsm_clock,
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.channel_map = vc5_hdmi_channel_map,
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};
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@@ -1797,6 +1816,7 @@ static const struct vc4_hdmi_variant bcm
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.phy_rng_enable = vc5_hdmi_phy_rng_enable,
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.phy_rng_disable = vc5_hdmi_phy_rng_disable,
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.get_hsm_clock = vc5_hdmi_get_hsm_clock,
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+ .calc_hsm_clock = vc5_hdmi_calc_hsm_clock,
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.channel_map = vc5_hdmi_channel_map,
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};
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--- a/drivers/gpu/drm/vc4/vc4_hdmi.h
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+++ b/drivers/gpu/drm/vc4/vc4_hdmi.h
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@@ -92,6 +92,9 @@ struct vc4_hdmi_variant {
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/* Callback to get hsm clock */
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u32 (*get_hsm_clock)(struct vc4_hdmi *vc4_hdmi);
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+ /* Callback to get hsm clock */
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+ u32 (*calc_hsm_clock)(struct vc4_hdmi *vc4_hdmi, unsigned long pixel_rate);
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+
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/* Callback to get channel map */
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u32 (*channel_map)(struct vc4_hdmi *vc4_hdmi, u32 channel_mask);
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};
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