164 lines
5.3 KiB
Diff
164 lines
5.3 KiB
Diff
From 3c33724058852d7c58d77d03e11ca545fb04256a Mon Sep 17 00:00:00 2001
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From: Maxime Ripard <maxime@cerno.tech>
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Date: Mon, 10 Feb 2020 15:23:06 +0100
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Subject: [PATCH] drm/vc4: hdmi: Adjust HSM clock rate depending on
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pixel rate
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The HSM clock needs to be setup at around 110% of the pixel rate. This
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was done previously by setting the clock rate to 148.5MHz * 108% at
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probe time and only check in mode_valid whether the mode pixel clock was
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under 148.5MHz or not.
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However, with 4k we need to change that frequency to a higher frequency
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than 148.5MHz.
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Let's change that logic a bit by setting the clock rate of the HSM clock
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to the pixel rate at encoder_enable time. This would work for the
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BCM2711 that support 4k resolutions and has a clock that can provide it,
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but we still have to take care of a 4k panel plugged on a BCM283x SoCs
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that wouldn't be able to use those modes, so let's define the limit in
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the variant.
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Signed-off-by: Maxime Ripard <maxime@cerno.tech>
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---
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drivers/gpu/drm/vc4/vc4_hdmi.c | 51 +++++++++++++++++-----------------
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drivers/gpu/drm/vc4/vc4_hdmi.h | 3 ++
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2 files changed, 29 insertions(+), 25 deletions(-)
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--- a/drivers/gpu/drm/vc4/vc4_hdmi.c
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+++ b/drivers/gpu/drm/vc4/vc4_hdmi.c
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@@ -52,7 +52,6 @@
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#include "vc4_hdmi_regs.h"
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#include "vc4_regs.h"
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-#define HSM_CLOCK_FREQ 163682864
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#define CEC_CLOCK_FREQ 40000
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static int vc4_hdmi_debugfs_regs(struct seq_file *m, void *unused)
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@@ -329,6 +328,7 @@ static void vc4_hdmi_encoder_disable(str
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HDMI_WRITE(HDMI_VID_CTL,
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HDMI_READ(HDMI_VID_CTL) & ~VC4_HD_VID_CTL_ENABLE);
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+ clk_disable_unprepare(vc4_hdmi->hsm_clock);
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clk_disable_unprepare(vc4_hdmi->pixel_clock);
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ret = pm_runtime_put(&vc4_hdmi->pdev->dev);
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@@ -426,6 +426,7 @@ static void vc4_hdmi_encoder_enable(stru
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struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
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struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder);
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bool debug_dump_regs = false;
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+ unsigned long pixel_rate, hsm_rate;
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int ret;
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ret = pm_runtime_get_sync(&vc4_hdmi->pdev->dev);
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@@ -434,9 +435,8 @@ static void vc4_hdmi_encoder_enable(stru
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return;
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}
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- ret = clk_set_rate(vc4_hdmi->pixel_clock,
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- mode->clock * 1000 *
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- ((mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1));
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+ pixel_rate = mode->clock * 1000 * ((mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1);
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+ ret = clk_set_rate(vc4_hdmi->pixel_clock, pixel_rate);
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if (ret) {
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DRM_ERROR("Failed to set pixel clock rate: %d\n", ret);
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return;
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@@ -448,6 +448,24 @@ static void vc4_hdmi_encoder_enable(stru
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return;
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}
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+ /*
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+ * The HSM rate needs to be at 108% of the pixel clock, with a
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+ * minimum of 108MHz.
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+ */
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+ hsm_rate = max_t(unsigned long, 108000000, (pixel_rate / 100) * 108);
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+ ret = clk_set_rate(vc4_hdmi->hsm_clock, hsm_rate);
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+ if (ret) {
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+ DRM_ERROR("Failed to set HSM clock rate: %d\n", ret);
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+ return;
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+ }
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+
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+ ret = clk_prepare_enable(vc4_hdmi->hsm_clock);
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+ if (ret) {
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+ DRM_ERROR("Failed to turn on HSM clock: %d\n", ret);
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+ clk_disable_unprepare(vc4_hdmi->pixel_clock);
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+ return;
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+ }
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+
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if (vc4_hdmi->variant->reset)
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vc4_hdmi->variant->reset(vc4_hdmi);
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@@ -578,7 +596,9 @@ vc4_hdmi_encoder_mode_valid(struct drm_e
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* Additionally, the AXI clock needs to be at least 25% of
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* pixel clock, but HSM ends up being the limiting factor.
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*/
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- if (mode->clock > HSM_CLOCK_FREQ / (1000 * 101 / 100))
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+ struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
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+
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+ if ((mode->clock * 1000) > vc4_hdmi->variant->max_pixel_clock)
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return MODE_CLOCK_HIGH;
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return MODE_OK;
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@@ -1354,23 +1374,6 @@ static int vc4_hdmi_bind(struct device *
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return -EPROBE_DEFER;
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}
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- /* This is the rate that is set by the firmware. The number
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- * needs to be a bit higher than the pixel clock rate
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- * (generally 148.5Mhz).
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- */
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- ret = clk_set_rate(vc4_hdmi->hsm_clock, HSM_CLOCK_FREQ);
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- if (ret) {
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- DRM_ERROR("Failed to set HSM clock rate: %d\n", ret);
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- goto err_put_i2c;
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- }
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-
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- ret = clk_prepare_enable(vc4_hdmi->hsm_clock);
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- if (ret) {
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- DRM_ERROR("Failed to turn on HDMI state machine clock: %d\n",
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- ret);
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- goto err_put_i2c;
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- }
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-
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/* Only use the GPIO HPD pin if present in the DT, otherwise
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* we'll use the HDMI core's register.
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*/
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@@ -1428,9 +1431,7 @@ err_destroy_conn:
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err_destroy_encoder:
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vc4_hdmi_encoder_destroy(encoder);
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err_unprepare_hsm:
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- clk_disable_unprepare(vc4_hdmi->hsm_clock);
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pm_runtime_disable(dev);
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-err_put_i2c:
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put_device(&vc4_hdmi->ddc->dev);
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return ret;
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@@ -1453,7 +1454,6 @@ static void vc4_hdmi_unbind(struct devic
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vc4_hdmi_connector_destroy(&vc4_hdmi->connector);
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vc4_hdmi_encoder_destroy(&vc4_hdmi->encoder.base.base);
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- clk_disable_unprepare(vc4_hdmi->hsm_clock);
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pm_runtime_disable(dev);
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put_device(&vc4_hdmi->ddc->dev);
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@@ -1476,6 +1476,7 @@ static int vc4_hdmi_dev_remove(struct pl
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}
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static const struct vc4_hdmi_variant bcm2835_variant = {
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+ .max_pixel_clock = 148500000,
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.audio_available = true,
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.cec_available = true,
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.registers = vc4_hdmi_fields,
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--- a/drivers/gpu/drm/vc4/vc4_hdmi.h
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+++ b/drivers/gpu/drm/vc4/vc4_hdmi.h
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@@ -38,6 +38,9 @@ struct vc4_hdmi_variant {
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/* Set to true when the CEC support is available */
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bool cec_available;
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+ /* Maximum pixel clock supported by the controller (in Hz) */
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+ unsigned long long max_pixel_clock;
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+
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/* List of the registers available on that variant */
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const struct vc4_hdmi_register *registers;
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