134 lines
4.7 KiB
Diff
134 lines
4.7 KiB
Diff
From b9c57901c600e09b100942b637c6bb01e52b7326 Mon Sep 17 00:00:00 2001
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From: Maxime Ripard <maxime@cerno.tech>
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Date: Mon, 6 Jan 2020 13:43:27 +0100
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Subject: [PATCH] drm/vc4: hdmi: Add a set_timings callback
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Similarly to the previous patches, the timings setup in the HDMI controller
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of the BCM2711 is slightly different, mostly because it supports higher
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resolutions and thus needed more spaces for the various timings, resulting
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in the register layout changing.
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Let's add a callback for that as well.
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Signed-off-by: Maxime Ripard <maxime@cerno.tech>
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---
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drivers/gpu/drm/vc4/vc4_hdmi.c | 71 +++++++++++++++++++---------------
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drivers/gpu/drm/vc4/vc4_hdmi.h | 4 ++
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2 files changed, 44 insertions(+), 31 deletions(-)
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--- a/drivers/gpu/drm/vc4/vc4_hdmi.c
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+++ b/drivers/gpu/drm/vc4/vc4_hdmi.c
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@@ -372,12 +372,9 @@ static void vc4_hdmi_csc_setup(struct vc
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HDMI_WRITE(HDMI_CSC_CTL, csc_ctl);
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}
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-static void vc4_hdmi_encoder_enable(struct drm_encoder *encoder)
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+static void vc4_hdmi_set_timings(struct vc4_hdmi *vc4_hdmi,
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+ struct drm_display_mode *mode)
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{
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- struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode;
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- struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
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- struct vc4_hdmi_encoder *vc4_encoder = &vc4_hdmi->encoder;
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- bool debug_dump_regs = false;
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bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC;
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bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC;
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bool interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
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@@ -395,6 +392,41 @@ static void vc4_hdmi_encoder_enable(stru
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mode->crtc_vsync_end -
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interlaced,
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VC4_HDMI_VERTB_VBP));
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+
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+ HDMI_WRITE(HDMI_HORZA,
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+ (vsync_pos ? VC4_HDMI_HORZA_VPOS : 0) |
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+ (hsync_pos ? VC4_HDMI_HORZA_HPOS : 0) |
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+ VC4_SET_FIELD(mode->hdisplay * pixel_rep,
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+ VC4_HDMI_HORZA_HAP));
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+
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+ HDMI_WRITE(HDMI_HORZB,
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+ VC4_SET_FIELD((mode->htotal -
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+ mode->hsync_end) * pixel_rep,
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+ VC4_HDMI_HORZB_HBP) |
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+ VC4_SET_FIELD((mode->hsync_end -
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+ mode->hsync_start) * pixel_rep,
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+ VC4_HDMI_HORZB_HSP) |
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+ VC4_SET_FIELD((mode->hsync_start -
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+ mode->hdisplay) * pixel_rep,
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+ VC4_HDMI_HORZB_HFP));
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+
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+ HDMI_WRITE(HDMI_VERTA0, verta);
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+ HDMI_WRITE(HDMI_VERTA1, verta);
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+
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+ HDMI_WRITE(HDMI_VERTB0, vertb_even);
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+ HDMI_WRITE(HDMI_VERTB1, vertb);
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+
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+ HDMI_WRITE(HDMI_VID_CTL,
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+ (vsync_pos ? 0 : VC4_HD_VID_CTL_VSYNC_LOW) |
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+ (hsync_pos ? 0 : VC4_HD_VID_CTL_HSYNC_LOW));
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+}
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+
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+static void vc4_hdmi_encoder_enable(struct drm_encoder *encoder)
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+{
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+ struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode;
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+ struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
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+ struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder);
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+ bool debug_dump_regs = false;
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int ret;
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ret = pm_runtime_get_sync(&vc4_hdmi->pdev->dev);
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@@ -438,32 +470,8 @@ static void vc4_hdmi_encoder_enable(stru
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VC4_HDMI_SCHEDULER_CONTROL_MANUAL_FORMAT |
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VC4_HDMI_SCHEDULER_CONTROL_IGNORE_VSYNC_PREDICTS);
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- HDMI_WRITE(HDMI_HORZA,
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- (vsync_pos ? VC4_HDMI_HORZA_VPOS : 0) |
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- (hsync_pos ? VC4_HDMI_HORZA_HPOS : 0) |
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- VC4_SET_FIELD(mode->hdisplay * pixel_rep,
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- VC4_HDMI_HORZA_HAP));
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-
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- HDMI_WRITE(HDMI_HORZB,
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- VC4_SET_FIELD((mode->htotal -
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- mode->hsync_end) * pixel_rep,
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- VC4_HDMI_HORZB_HBP) |
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- VC4_SET_FIELD((mode->hsync_end -
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- mode->hsync_start) * pixel_rep,
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- VC4_HDMI_HORZB_HSP) |
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- VC4_SET_FIELD((mode->hsync_start -
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- mode->hdisplay) * pixel_rep,
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- VC4_HDMI_HORZB_HFP));
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-
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- HDMI_WRITE(HDMI_VERTA0, verta);
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- HDMI_WRITE(HDMI_VERTA1, verta);
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-
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- HDMI_WRITE(HDMI_VERTB0, vertb_even);
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- HDMI_WRITE(HDMI_VERTB1, vertb);
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-
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- HDMI_WRITE(HDMI_VID_CTL,
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- (vsync_pos ? 0 : VC4_HD_VID_CTL_VSYNC_LOW) |
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- (hsync_pos ? 0 : VC4_HD_VID_CTL_HSYNC_LOW));
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+ if (vc4_hdmi->variant->set_timings)
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+ vc4_hdmi->variant->set_timings(vc4_hdmi, mode);
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if (vc4_encoder->hdmi_monitor &&
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drm_default_rgb_quant_range(mode) == HDMI_QUANTIZATION_RANGE_LIMITED) {
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@@ -1441,6 +1449,7 @@ static const struct vc4_hdmi_variant bcm
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.init_resources = vc4_hdmi_init_resources,
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.csc_setup = vc4_hdmi_csc_setup,
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.reset = vc4_hdmi_reset,
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+ .set_timings = vc4_hdmi_set_timings,
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.phy_init = vc4_hdmi_phy_init,
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.phy_disable = vc4_hdmi_phy_disable,
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.phy_rng_enable = vc4_hdmi_phy_rng_enable,
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--- a/drivers/gpu/drm/vc4/vc4_hdmi.h
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+++ b/drivers/gpu/drm/vc4/vc4_hdmi.h
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@@ -44,6 +44,10 @@ struct vc4_hdmi_variant {
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/* Callback to enable / disable the CSC */
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void (*csc_setup)(struct vc4_hdmi *vc4_hdmi, bool enable);
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+ /* Callback to configure the video timings in the HDMI block */
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+ void (*set_timings)(struct vc4_hdmi *vc4_hdmi,
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+ struct drm_display_mode *mode);
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+
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/* Callback to initialize the PHY according to the mode */
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void (*phy_init)(struct vc4_hdmi *vc4_hdmi,
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struct drm_display_mode *mode);
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