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https://git.openwrt.org/openwrt/openwrt.git
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8299d1f057
Rebased RPi foundation patches on linux 5.10.59, removed applied and reverted patches, wireless patches and defconfig patches. bcm2708: boot tested on RPi B+ v1.2 bcm2709: boot tested on RPi 4B v1.1 4G bcm2711: boot tested on RPi 4B v1.1 4G Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
257 lines
7.4 KiB
Diff
257 lines
7.4 KiB
Diff
From f30e24aa4a64cb6c341140270b74357505a20d4f Mon Sep 17 00:00:00 2001
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From: John Cox <jc@kynesim.co.uk>
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Date: Thu, 8 Apr 2021 18:34:09 +0100
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Subject: [PATCH] media: rpivid: Improve SPS/PPS error
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handling/validation
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Move size and width checking from bitstream processing to control
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validation
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Signed-off-by: John Cox <jc@kynesim.co.uk>
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---
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drivers/staging/media/rpivid/rpivid.c | 5 +-
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drivers/staging/media/rpivid/rpivid.h | 6 +-
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drivers/staging/media/rpivid/rpivid_h265.c | 132 ++++++++++++++++++---
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3 files changed, 121 insertions(+), 22 deletions(-)
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--- a/drivers/staging/media/rpivid/rpivid.c
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+++ b/drivers/staging/media/rpivid/rpivid.c
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@@ -38,12 +38,14 @@ static const struct rpivid_control rpivi
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{
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.cfg = {
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.id = V4L2_CID_MPEG_VIDEO_HEVC_SPS,
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+ .ops = &rpivid_hevc_sps_ctrl_ops,
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},
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.required = true,
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},
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{
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.cfg = {
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.id = V4L2_CID_MPEG_VIDEO_HEVC_PPS,
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+ .ops = &rpivid_hevc_pps_ctrl_ops,
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},
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.required = true,
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},
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@@ -119,7 +121,7 @@ static int rpivid_init_ctrls(struct rpiv
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for (i = 0; i < rpivid_ctrls_COUNT; i++) {
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ctrl = v4l2_ctrl_new_custom(hdl, &rpivid_ctrls[i].cfg,
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- NULL);
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+ ctx);
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if (hdl->error) {
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v4l2_err(&dev->v4l2_dev,
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"Failed to create new custom control id=%#x\n",
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@@ -191,6 +193,7 @@ static int rpivid_request_validate(struc
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if (!ctrl_test) {
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v4l2_info(&ctx->dev->v4l2_dev,
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"Missing required codec control\n");
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+ v4l2_ctrl_request_hdl_put(hdl);
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return -ENOENT;
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}
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}
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--- a/drivers/staging/media/rpivid/rpivid.h
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+++ b/drivers/staging/media/rpivid/rpivid.h
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@@ -185,7 +185,7 @@ struct rpivid_dev {
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struct platform_device *pdev;
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struct device *dev;
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struct v4l2_m2m_dev *m2m_dev;
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- struct rpivid_dec_ops *dec_ops;
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+ const struct rpivid_dec_ops *dec_ops;
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/* Device file mutex */
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struct mutex dev_mutex;
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@@ -201,7 +201,9 @@ struct rpivid_dev {
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struct rpivid_hw_irq_ctrl ic_active2;
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};
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-extern struct rpivid_dec_ops rpivid_dec_ops_h265;
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+extern const struct rpivid_dec_ops rpivid_dec_ops_h265;
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+extern const struct v4l2_ctrl_ops rpivid_hevc_sps_ctrl_ops;
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+extern const struct v4l2_ctrl_ops rpivid_hevc_pps_ctrl_ops;
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struct v4l2_ctrl *rpivid_find_ctrl(struct rpivid_ctx *ctx, u32 id);
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void *rpivid_find_control_data(struct rpivid_ctx *ctx, u32 id);
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--- a/drivers/staging/media/rpivid/rpivid_h265.c
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+++ b/drivers/staging/media/rpivid/rpivid_h265.c
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@@ -1432,9 +1432,13 @@ static int updated_ps(struct rpivid_dec_
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s->ctb_addr_rs_to_ts = kmalloc_array(s->ctb_size,
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sizeof(*s->ctb_addr_rs_to_ts),
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GFP_KERNEL);
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+ if (!s->ctb_addr_rs_to_ts)
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+ goto fail;
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s->ctb_addr_ts_to_rs = kmalloc_array(s->ctb_size,
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sizeof(*s->ctb_addr_ts_to_rs),
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GFP_KERNEL);
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+ if (!s->ctb_addr_ts_to_rs)
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+ goto fail;
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if (!(s->pps.flags & V4L2_HEVC_PPS_FLAG_TILES_ENABLED)) {
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s->tile_width = 1;
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@@ -1446,8 +1450,12 @@ static int updated_ps(struct rpivid_dec_
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s->col_bd = kmalloc((s->tile_width + 1) * sizeof(*s->col_bd),
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GFP_KERNEL);
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+ if (!s->col_bd)
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+ goto fail;
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s->row_bd = kmalloc((s->tile_height + 1) * sizeof(*s->row_bd),
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GFP_KERNEL);
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+ if (!s->row_bd)
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+ goto fail;
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s->col_bd[0] = 0;
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for (i = 1; i < s->tile_width; i++)
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@@ -1462,8 +1470,13 @@ static int updated_ps(struct rpivid_dec_
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s->row_bd[s->tile_height] = s->ctb_height;
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fill_rs_to_ts(s);
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-
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return 0;
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+
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+fail:
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+ free_ps_info(s);
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+ /* Set invalid to force reload */
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+ s->sps.pic_width_in_luma_samples = 0;
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+ return -ENOMEM;
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}
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static int write_cmd_buffer(struct rpivid_dev *const dev,
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@@ -1694,7 +1707,9 @@ static void rpivid_h265_setup(struct rpi
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memcpy(&s->pps, run->h265.pps, sizeof(s->pps));
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/* Recalc stuff as required */
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- updated_ps(s);
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+ rv = updated_ps(s);
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+ if (rv)
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+ goto fail;
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}
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de = dec_env_new(ctx);
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@@ -1772,22 +1787,6 @@ static void rpivid_h265_setup(struct rpi
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goto fail;
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}
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- if (s->sps.pic_width_in_luma_samples > 4096 ||
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- s->sps.pic_height_in_luma_samples > 4096) {
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- v4l2_warn(&dev->v4l2_dev,
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- "Pic dimension (%dx%d) exeeds 4096\n",
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- s->sps.pic_width_in_luma_samples,
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- s->sps.pic_height_in_luma_samples);
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- goto fail;
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- }
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- if ((s->tile_width != 1 || s->tile_height != 1) &&
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- (s->pps.flags &
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- V4L2_HEVC_PPS_FLAG_ENTROPY_CODING_SYNC_ENABLED)) {
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- v4l2_warn(&dev->v4l2_dev,
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- "Tiles + WPP not supported\n");
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- goto fail;
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- }
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-
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// Fill in ref planes with our address s.t. if we mess
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// up refs somehow then we still have a valid address
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// entry
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@@ -2515,9 +2514,104 @@ static void rpivid_h265_trigger(struct r
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}
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}
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-struct rpivid_dec_ops rpivid_dec_ops_h265 = {
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+const struct rpivid_dec_ops rpivid_dec_ops_h265 = {
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.setup = rpivid_h265_setup,
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.start = rpivid_h265_start,
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.stop = rpivid_h265_stop,
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.trigger = rpivid_h265_trigger,
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};
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+
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+static int try_ctrl_sps(struct v4l2_ctrl *ctrl)
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+{
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+ const struct v4l2_ctrl_hevc_sps *const sps = ctrl->p_new.p_hevc_sps;
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+ struct rpivid_ctx *const ctx = ctrl->priv;
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+ struct rpivid_dev *const dev = ctx->dev;
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+
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+ if (sps->chroma_format_idc != 1) {
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+ v4l2_warn(&dev->v4l2_dev,
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+ "Chroma format (%d) unsupported\n",
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+ sps->chroma_format_idc);
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+ return -EINVAL;
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+ }
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+
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+ if (sps->bit_depth_luma_minus8 != 0 &&
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+ sps->bit_depth_luma_minus8 != 2) {
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+ v4l2_warn(&dev->v4l2_dev,
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+ "Luma depth (%d) unsupported\n",
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+ sps->bit_depth_luma_minus8 + 8);
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+ return -EINVAL;
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+ }
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+
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+ if (sps->bit_depth_luma_minus8 != sps->bit_depth_chroma_minus8) {
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+ v4l2_warn(&dev->v4l2_dev,
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+ "Chroma depth (%d) != Luma depth (%d)\n",
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+ sps->bit_depth_chroma_minus8 + 8,
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+ sps->bit_depth_luma_minus8 + 8);
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+ return -EINVAL;
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+ }
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+
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+ if (!sps->pic_width_in_luma_samples ||
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+ !sps->pic_height_in_luma_samples ||
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+ sps->pic_width_in_luma_samples > 4096 ||
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+ sps->pic_height_in_luma_samples > 4096) {
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+ v4l2_warn(&dev->v4l2_dev,
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+ "Bad sps width (%u) x height (%u)\n",
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+ sps->pic_width_in_luma_samples,
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+ sps->pic_height_in_luma_samples);
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+ return -EINVAL;
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+ }
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+
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+ if (!ctx->dst_fmt_set)
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+ return 0;
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+
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+ if ((sps->bit_depth_luma_minus8 == 0 &&
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+ ctx->dst_fmt.pixelformat != V4L2_PIX_FMT_NV12_COL128) ||
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+ (sps->bit_depth_luma_minus8 == 2 &&
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+ ctx->dst_fmt.pixelformat != V4L2_PIX_FMT_NV12_10_COL128)) {
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+ v4l2_warn(&dev->v4l2_dev,
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+ "SPS luma depth %d does not match capture format\n",
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+ sps->bit_depth_luma_minus8 + 8);
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+ return -EINVAL;
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+ }
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+
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+ if (sps->pic_width_in_luma_samples > ctx->dst_fmt.width ||
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+ sps->pic_height_in_luma_samples > ctx->dst_fmt.height) {
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+ v4l2_warn(&dev->v4l2_dev,
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+ "SPS size (%dx%d) > capture size (%d,%d)\n",
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+ sps->pic_width_in_luma_samples,
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+ sps->pic_height_in_luma_samples,
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+ ctx->dst_fmt.width,
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+ ctx->dst_fmt.height);
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+ return -EINVAL;
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+ }
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+
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+ return 0;
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+}
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+
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+const struct v4l2_ctrl_ops rpivid_hevc_sps_ctrl_ops = {
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+ .try_ctrl = try_ctrl_sps,
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+};
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+
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+static int try_ctrl_pps(struct v4l2_ctrl *ctrl)
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+{
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+ const struct v4l2_ctrl_hevc_pps *const pps = ctrl->p_new.p_hevc_pps;
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+ struct rpivid_ctx *const ctx = ctrl->priv;
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+ struct rpivid_dev *const dev = ctx->dev;
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+
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+ if ((pps->flags &
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+ V4L2_HEVC_PPS_FLAG_ENTROPY_CODING_SYNC_ENABLED) &&
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+ (pps->flags &
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+ V4L2_HEVC_PPS_FLAG_TILES_ENABLED) &&
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+ (pps->num_tile_columns_minus1 || pps->num_tile_rows_minus1)) {
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+ v4l2_warn(&dev->v4l2_dev,
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+ "WPP + Tiles not supported\n");
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+ return -EINVAL;
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+ }
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+
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+ return 0;
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+}
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+
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+const struct v4l2_ctrl_ops rpivid_hevc_pps_ctrl_ops = {
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+ .try_ctrl = try_ctrl_pps,
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+};
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+
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