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8299d1f057
Rebased RPi foundation patches on linux 5.10.59, removed applied and reverted patches, wireless patches and defconfig patches. bcm2708: boot tested on RPi B+ v1.2 bcm2709: boot tested on RPi 4B v1.1 4G bcm2711: boot tested on RPi 4B v1.1 4G Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
67 lines
2.2 KiB
Diff
67 lines
2.2 KiB
Diff
From 7fe646b726b66c16f731e36e95d7eda9f182ba4d Mon Sep 17 00:00:00 2001
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From: Maxime Ripard <maxime@cerno.tech>
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Date: Thu, 3 Dec 2020 14:25:38 +0100
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Subject: [PATCH] drm/vc4: dsi: Use snprintf for the PHY clocks instead
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of an array
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Commit dc0bf36401e891c853e0a25baeb4e0b4e6f3626d upstream.
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The DSI clocks setup function has been using an array to store the clock
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name of either the DSI0 or DSI1 blocks, using the port ID to choose the
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proper one.
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Let's switch to an snprintf call to do the same thing and simplify the
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array a bit.
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Reviewed-by: Dave Stevenson <dave.stevenson@raspberrypi.com>
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Signed-off-by: Maxime Ripard <maxime@cerno.tech>
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Link: https://patchwork.freedesktop.org/patch/msgid/20201203132543.861591-4-maxime@cerno.tech
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---
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drivers/gpu/drm/vc4/vc4_dsi.c | 17 +++++++++--------
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1 file changed, 9 insertions(+), 8 deletions(-)
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--- a/drivers/gpu/drm/vc4/vc4_dsi.c
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+++ b/drivers/gpu/drm/vc4/vc4_dsi.c
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@@ -1390,12 +1390,12 @@ vc4_dsi_init_phy_clocks(struct vc4_dsi *
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struct device *dev = &dsi->pdev->dev;
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const char *parent_name = __clk_get_name(dsi->pll_phy_clock);
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static const struct {
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- const char *dsi0_name, *dsi1_name;
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+ const char *name;
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int div;
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} phy_clocks[] = {
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- { "dsi0_byte", "dsi1_byte", 8 },
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- { "dsi0_ddr2", "dsi1_ddr2", 4 },
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- { "dsi0_ddr", "dsi1_ddr", 2 },
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+ { "byte", 8 },
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+ { "ddr2", 4 },
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+ { "ddr", 2 },
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};
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int i;
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@@ -1411,8 +1411,12 @@ vc4_dsi_init_phy_clocks(struct vc4_dsi *
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for (i = 0; i < ARRAY_SIZE(phy_clocks); i++) {
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struct clk_fixed_factor *fix = &dsi->phy_clocks[i];
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struct clk_init_data init;
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+ char clk_name[16];
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int ret;
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+ snprintf(clk_name, sizeof(clk_name),
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+ "dsi%u_%s", dsi->port, phy_clocks[i].name);
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+
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/* We just use core fixed factor clock ops for the PHY
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* clocks. The clocks are actually gated by the
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* PHY_AFEC0_DDRCLK_EN bits, which we should be
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@@ -1429,10 +1433,7 @@ vc4_dsi_init_phy_clocks(struct vc4_dsi *
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memset(&init, 0, sizeof(init));
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init.parent_names = &parent_name;
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init.num_parents = 1;
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- if (dsi->port == 1)
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- init.name = phy_clocks[i].dsi1_name;
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- else
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- init.name = phy_clocks[i].dsi0_name;
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+ init.name = clk_name;
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init.ops = &clk_fixed_factor_ops;
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ret = devm_clk_hw_register(dev, &fix->hw);
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