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https://git.openwrt.org/openwrt/openwrt.git
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8299d1f057
Rebased RPi foundation patches on linux 5.10.59, removed applied and reverted patches, wireless patches and defconfig patches. bcm2708: boot tested on RPi B+ v1.2 bcm2709: boot tested on RPi 4B v1.1 4G bcm2711: boot tested on RPi 4B v1.1 4G Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
103 lines
3.9 KiB
Diff
103 lines
3.9 KiB
Diff
From 6d15419acb9914041e90bc88044d87bbcdcfec00 Mon Sep 17 00:00:00 2001
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From: Maxime Ripard <maxime@cerno.tech>
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Date: Tue, 15 Dec 2020 16:42:41 +0100
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Subject: [PATCH] drm/vc4: hdmi: Use the connector state pixel rate for
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the PHY
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The PHY initialisation parameters are not based on the pixel clock but
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the TMDS clock rate which can be the pixel clock in the standard case,
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but could be adjusted based on some parameters like the bits per color.
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Since the TMDS clock rate is stored in our custom connector state
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already, let's reuse it from there instead of computing it again.
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Acked-by: Thomas Zimmermann <tzimmermann@suse.de>
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Reviewed-by: Dave Stevenson <dave.stevenson@raspberrypi.com>
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Signed-off-by: Maxime Ripard <maxime@cerno.tech>
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---
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drivers/gpu/drm/vc4/vc4_hdmi.c | 2 +-
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drivers/gpu/drm/vc4/vc4_hdmi.h | 11 +++++------
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drivers/gpu/drm/vc4/vc4_hdmi_phy.c | 8 +++++---
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3 files changed, 11 insertions(+), 10 deletions(-)
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--- a/drivers/gpu/drm/vc4/vc4_hdmi.c
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+++ b/drivers/gpu/drm/vc4/vc4_hdmi.c
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@@ -761,7 +761,7 @@ static void vc4_hdmi_encoder_pre_crtc_co
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}
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if (vc4_hdmi->variant->phy_init)
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- vc4_hdmi->variant->phy_init(vc4_hdmi, mode);
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+ vc4_hdmi->variant->phy_init(vc4_hdmi, vc4_conn_state);
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HDMI_WRITE(HDMI_SCHEDULER_CONTROL,
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HDMI_READ(HDMI_SCHEDULER_CONTROL) |
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--- a/drivers/gpu/drm/vc4/vc4_hdmi.h
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+++ b/drivers/gpu/drm/vc4/vc4_hdmi.h
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@@ -21,10 +21,9 @@ to_vc4_hdmi_encoder(struct drm_encoder *
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return container_of(encoder, struct vc4_hdmi_encoder, base.base);
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}
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-struct drm_display_mode;
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-
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struct vc4_hdmi;
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struct vc4_hdmi_register;
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+struct vc4_hdmi_connector_state;
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enum vc4_hdmi_phy_channel {
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PHY_LANE_0 = 0,
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@@ -77,9 +76,9 @@ struct vc4_hdmi_variant {
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void (*set_timings)(struct vc4_hdmi *vc4_hdmi,
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struct drm_display_mode *mode);
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- /* Callback to initialize the PHY according to the mode */
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+ /* Callback to initialize the PHY according to the connector state */
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void (*phy_init)(struct vc4_hdmi *vc4_hdmi,
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- struct drm_display_mode *mode);
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+ struct vc4_hdmi_connector_state *vc4_conn_state);
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/* Callback to disable the PHY */
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void (*phy_disable)(struct vc4_hdmi *vc4_hdmi);
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@@ -199,13 +198,13 @@ conn_state_to_vc4_hdmi_conn_state(struct
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}
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void vc4_hdmi_phy_init(struct vc4_hdmi *vc4_hdmi,
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- struct drm_display_mode *mode);
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+ struct vc4_hdmi_connector_state *vc4_conn_state);
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void vc4_hdmi_phy_disable(struct vc4_hdmi *vc4_hdmi);
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void vc4_hdmi_phy_rng_enable(struct vc4_hdmi *vc4_hdmi);
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void vc4_hdmi_phy_rng_disable(struct vc4_hdmi *vc4_hdmi);
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void vc5_hdmi_phy_init(struct vc4_hdmi *vc4_hdmi,
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- struct drm_display_mode *mode);
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+ struct vc4_hdmi_connector_state *vc4_conn_state);
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void vc5_hdmi_phy_disable(struct vc4_hdmi *vc4_hdmi);
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void vc5_hdmi_phy_rng_enable(struct vc4_hdmi *vc4_hdmi);
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void vc5_hdmi_phy_rng_disable(struct vc4_hdmi *vc4_hdmi);
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--- a/drivers/gpu/drm/vc4/vc4_hdmi_phy.c
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+++ b/drivers/gpu/drm/vc4/vc4_hdmi_phy.c
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@@ -127,7 +127,8 @@
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#define OSCILLATOR_FREQUENCY 54000000
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-void vc4_hdmi_phy_init(struct vc4_hdmi *vc4_hdmi, struct drm_display_mode *mode)
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+void vc4_hdmi_phy_init(struct vc4_hdmi *vc4_hdmi,
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+ struct vc4_hdmi_connector_state *conn_state)
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{
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/* PHY should be in reset, like
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* vc4_hdmi_encoder_disable() does.
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@@ -339,11 +340,12 @@ static void vc5_hdmi_reset_phy(struct vc
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HDMI_WRITE(HDMI_TX_PHY_POWERDOWN_CTL, BIT(10));
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}
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-void vc5_hdmi_phy_init(struct vc4_hdmi *vc4_hdmi, struct drm_display_mode *mode)
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+void vc5_hdmi_phy_init(struct vc4_hdmi *vc4_hdmi,
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+ struct vc4_hdmi_connector_state *conn_state)
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{
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const struct phy_lane_settings *chan0_settings, *chan1_settings, *chan2_settings, *clock_settings;
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const struct vc4_hdmi_variant *variant = vc4_hdmi->variant;
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- unsigned long long pixel_freq = mode->clock * 1000;
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+ unsigned long long pixel_freq = conn_state->pixel_rate;
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unsigned long long vco_freq;
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unsigned char word_sel;
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u8 vco_sel, vco_div;
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