70 lines
2.4 KiB
Diff
70 lines
2.4 KiB
Diff
From 671b5b9af51bd5296d4fe76155b3ba75c99000b9 Mon Sep 17 00:00:00 2001
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From: Dave Stevenson <dave.stevenson@raspberrypi.com>
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Date: Mon, 13 Sep 2021 17:30:18 +0100
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Subject: [PATCH] drm/vc4: Reset HDMI MISC_CONTROL register.
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The HDMI block can repeat pixels for double clocked modes,
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and the firmware is now configuring the block to do this as
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the PV is doing it incorrectly when at 2pixels/clock.
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If the kernel doesn't reset it then we end up with strange
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modes.
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Reset MISC_CONTROL.
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Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>
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---
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drivers/gpu/drm/vc4/vc4_hdmi.c | 8 ++++++++
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drivers/gpu/drm/vc4/vc4_hdmi_regs.h | 3 +++
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2 files changed, 11 insertions(+)
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--- a/drivers/gpu/drm/vc4/vc4_hdmi.c
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+++ b/drivers/gpu/drm/vc4/vc4_hdmi.c
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@@ -79,6 +79,9 @@
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#define VC5_HDMI_VERTB_VSPO_SHIFT 16
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#define VC5_HDMI_VERTB_VSPO_MASK VC4_MASK(29, 16)
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+#define VC5_HDMI_MISC_CONTROL_PIXEL_REP_SHIFT 0
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+#define VC5_HDMI_MISC_CONTROL_PIXEL_REP_MASK VC4_MASK(3, 0)
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+
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#define VC5_HDMI_SCRAMBLER_CTL_ENABLE BIT(0)
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#define VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE_SHIFT 8
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@@ -963,6 +966,11 @@ static void vc5_hdmi_set_timings(struct
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reg |= gcp_en ? VC5_HDMI_GCP_CONFIG_GCP_ENABLE : 0;
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HDMI_WRITE(HDMI_GCP_CONFIG, reg);
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+ reg = HDMI_READ(HDMI_MISC_CONTROL);
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+ reg &= ~VC5_HDMI_MISC_CONTROL_PIXEL_REP_MASK;
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+ reg |= VC4_SET_FIELD(0, VC5_HDMI_MISC_CONTROL_PIXEL_REP);
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+ HDMI_WRITE(HDMI_MISC_CONTROL, reg);
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+
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HDMI_WRITE(HDMI_CLOCK_STOP, 0);
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spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
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--- a/drivers/gpu/drm/vc4/vc4_hdmi_regs.h
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+++ b/drivers/gpu/drm/vc4/vc4_hdmi_regs.h
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@@ -125,6 +125,7 @@ enum vc4_hdmi_field {
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HDMI_VERTB0,
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HDMI_VERTB1,
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HDMI_VID_CTL,
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+ HDMI_MISC_CONTROL,
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};
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struct vc4_hdmi_register {
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@@ -235,6 +236,7 @@ static const struct vc4_hdmi_register __
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VC4_HDMI_REG(HDMI_VERTB0, 0x0f0),
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VC4_HDMI_REG(HDMI_VERTA1, 0x0f4),
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VC4_HDMI_REG(HDMI_VERTB1, 0x0f8),
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+ VC4_HDMI_REG(HDMI_MISC_CONTROL, 0x100),
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VC4_HDMI_REG(HDMI_MAI_CHANNEL_MAP, 0x09c),
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VC4_HDMI_REG(HDMI_MAI_CONFIG, 0x0a0),
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VC4_HDMI_REG(HDMI_DEEP_COLOR_CONFIG_1, 0x170),
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@@ -315,6 +317,7 @@ static const struct vc4_hdmi_register __
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VC4_HDMI_REG(HDMI_VERTB0, 0x0f0),
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VC4_HDMI_REG(HDMI_VERTA1, 0x0f4),
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VC4_HDMI_REG(HDMI_VERTB1, 0x0f8),
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+ VC4_HDMI_REG(HDMI_MISC_CONTROL, 0x100),
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VC4_HDMI_REG(HDMI_MAI_CHANNEL_MAP, 0x09c),
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VC4_HDMI_REG(HDMI_MAI_CONFIG, 0x0a0),
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VC4_HDMI_REG(HDMI_DEEP_COLOR_CONFIG_1, 0x170),
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