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4cd5ce5a7f
Increase the SPI frequency for the MT7620 based TP-Link Archer series to 30MHz. TP-Link uses different SPI flash chips for the same board revision, so be conservative to not break boards with a different chip. 30MHz should be well supported by all chips. Tested on Archer C2 v1 (GD25Q64B) and Archer C20i (W25Q64FV). Archer C20i (before) ==================== root@OpenWrt:~# time dd if=/dev/mtd1 of=/tmp/test.bin bs=64k 122+0 records in 122+0 records out real 0m 15.30s user 0m 0.00s sys 0m 15.29s Archer C20i (after) =================== root@OpenWrt:~# time dd if=/dev/mtd1 of=/tmp/test.bin bs=64k 122+0 records in 122+0 records out real 0m 5.99s user 0m 0.00s sys 0m 5.98s Signed-off-by: David Bauer <mail@david-bauer.net> Acked-by: Adrian Schmutzler <freifunk@adrianschmutzler.de>
127 lines
1.7 KiB
Plaintext
127 lines
1.7 KiB
Plaintext
#include "mt7620a.dtsi"
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#include <dt-bindings/input/input.h>
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#include <dt-bindings/gpio/gpio.h>
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/ {
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chosen {
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bootargs = "console=ttyS0,115200";
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};
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keys {
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compatible = "gpio-keys";
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reset {
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label = "reset";
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gpios = <&gpio0 13 GPIO_ACTIVE_LOW>;
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linux,code = <KEY_RESTART>;
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};
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rfkill {
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label = "rfkill";
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gpios = <&gpio0 2 GPIO_ACTIVE_LOW>;
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linux,code = <KEY_RFKILL>;
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};
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};
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};
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&gpio1 {
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status = "okay";
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};
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&gpio2 {
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status = "okay";
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};
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&gpio3 {
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status = "okay";
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};
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&spi0 {
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status = "okay";
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flash@0 {
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compatible = "jedec,spi-nor";
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reg = <0>;
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spi-max-frequency = <30000000>;
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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partition@0 {
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label = "u-boot";
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reg = <0x0 0x20000>;
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read-only;
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};
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partition@20000 {
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compatible = "tplink,firmware";
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label = "firmware";
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reg = <0x20000 0x7a0000>;
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};
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partition@7c0000 {
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label = "config";
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reg = <0x7c0000 0x10000>;
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read-only;
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};
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rom: partition@7d0000 {
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label = "rom";
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reg = <0x7d0000 0x10000>;
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read-only;
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};
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partition@7e0000 {
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label = "romfile";
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reg = <0x7e0000 0x10000>;
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read-only;
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};
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radio: partition@7f0000 {
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label = "radio";
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reg = <0x7f0000 0x10000>;
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read-only;
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};
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};
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};
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};
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ðernet {
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pinctrl-names = "default";
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mtd-mac-address = <&rom 0xf100>;
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mediatek,portmap = "wllll";
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};
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&ehci {
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status = "okay";
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};
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&ohci {
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status = "okay";
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};
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&gsw {
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mediatek,port4 = "ephy";
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};
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&wmac {
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ralink,mtd-eeprom = <&radio 0x0>;
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};
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&pcie {
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status = "okay";
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};
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&pcie0 {
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wifi: mt76@0,0 {
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reg = <0x0000 0 0 0 0>;
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mediatek,mtd-eeprom = <&radio 0x8000>;
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ieee80211-freq-limit = <5000000 6000000>;
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};
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};
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