114 lines
4.0 KiB
Diff
114 lines
4.0 KiB
Diff
From 4833d6ea13a6d2c44a91247991a82c3eb6c1613e Mon Sep 17 00:00:00 2001
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From: Eugen Hristev <eugen.hristev@microchip.com>
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Date: Fri, 16 Oct 2020 12:39:18 +0300
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Subject: [PATCH 134/247] dmaengine: at_xdmac: add AXI priority support and
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recommended settings
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The sama7g5 version of the XDMAC supports priority configuration and
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outstanding capabilities.
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Add defines for the specific registers for this configuration, together
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with recommended settings.
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However the settings are very different if the XDMAC is a mem2mem or a
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per2mem controller.
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Thus, we need to differentiate according to device tree property.
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Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
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Link: https://lore.kernel.org/r/20201016093918.290137-1-eugen.hristev@microchip.com
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Signed-off-by: Vinod Koul <vkoul@kernel.org>
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---
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drivers/dma/at_xdmac.c | 47 ++++++++++++++++++++++++++++++++++++++++++
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1 file changed, 47 insertions(+)
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--- a/drivers/dma/at_xdmac.c
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+++ b/drivers/dma/at_xdmac.c
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@@ -30,7 +30,24 @@
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#define AT_XDMAC_FIFO_SZ(i) (((i) >> 5) & 0x7FF) /* Number of Bytes */
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#define AT_XDMAC_NB_REQ(i) ((((i) >> 16) & 0x3F) + 1) /* Number of Peripheral Requests Minus One */
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#define AT_XDMAC_GCFG 0x04 /* Global Configuration Register */
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+#define AT_XDMAC_WRHP(i) (((i) & 0xF) << 4)
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+#define AT_XDMAC_WRMP(i) (((i) & 0xF) << 8)
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+#define AT_XDMAC_WRLP(i) (((i) & 0xF) << 12)
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+#define AT_XDMAC_RDHP(i) (((i) & 0xF) << 16)
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+#define AT_XDMAC_RDMP(i) (((i) & 0xF) << 20)
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+#define AT_XDMAC_RDLP(i) (((i) & 0xF) << 24)
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+#define AT_XDMAC_RDSG(i) (((i) & 0xF) << 28)
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+#define AT_XDMAC_GCFG_M2M (AT_XDMAC_RDLP(0xF) | AT_XDMAC_WRLP(0xF))
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+#define AT_XDMAC_GCFG_P2M (AT_XDMAC_RDSG(0x1) | AT_XDMAC_RDHP(0x3) | \
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+ AT_XDMAC_WRHP(0x5))
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#define AT_XDMAC_GWAC 0x08 /* Global Weighted Arbiter Configuration Register */
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+#define AT_XDMAC_PW0(i) (((i) & 0xF) << 0)
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+#define AT_XDMAC_PW1(i) (((i) & 0xF) << 4)
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+#define AT_XDMAC_PW2(i) (((i) & 0xF) << 8)
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+#define AT_XDMAC_PW3(i) (((i) & 0xF) << 12)
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+#define AT_XDMAC_GWAC_M2M 0
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+#define AT_XDMAC_GWAC_P2M (AT_XDMAC_PW0(0xF) | AT_XDMAC_PW2(0xF))
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+
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#define AT_XDMAC_GIE 0x0C /* Global Interrupt Enable Register */
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#define AT_XDMAC_GID 0x10 /* Global Interrupt Disable Register */
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#define AT_XDMAC_GIM 0x14 /* Global Interrupt Mask Register */
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@@ -190,6 +207,8 @@ struct at_xdmac_layout {
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u8 chan_cc_reg_base;
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/* Source/Destination Interface must be specified or not */
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bool sdif;
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+ /* AXI queue priority configuration supported */
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+ bool axi_config;
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};
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/* ----- Channels ----- */
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@@ -268,6 +287,7 @@ static const struct at_xdmac_layout at_x
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.gswf = 0x40,
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.chan_cc_reg_base = 0x50,
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.sdif = true,
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+ .axi_config = false,
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};
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static const struct at_xdmac_layout at_xdmac_sama7g5_layout = {
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@@ -280,6 +300,7 @@ static const struct at_xdmac_layout at_x
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.gswf = 0x50,
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.chan_cc_reg_base = 0x60,
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.sdif = false,
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+ .axi_config = true,
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};
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static inline void __iomem *at_xdmac_chan_reg_base(struct at_xdmac *atxdmac, unsigned int chan_nb)
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@@ -2003,6 +2024,30 @@ static int atmel_xdmac_resume(struct dev
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}
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#endif /* CONFIG_PM_SLEEP */
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+static void at_xdmac_axi_config(struct platform_device *pdev)
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+{
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+ struct at_xdmac *atxdmac = (struct at_xdmac *)platform_get_drvdata(pdev);
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+ bool dev_m2m = false;
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+ u32 dma_requests;
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+
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+ if (!atxdmac->layout->axi_config)
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+ return; /* Not supported */
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+
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+ if (!of_property_read_u32(pdev->dev.of_node, "dma-requests",
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+ &dma_requests)) {
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+ dev_info(&pdev->dev, "controller in mem2mem mode.\n");
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+ dev_m2m = true;
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+ }
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+
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+ if (dev_m2m) {
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+ at_xdmac_write(atxdmac, AT_XDMAC_GCFG, AT_XDMAC_GCFG_M2M);
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+ at_xdmac_write(atxdmac, AT_XDMAC_GWAC, AT_XDMAC_GWAC_M2M);
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+ } else {
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+ at_xdmac_write(atxdmac, AT_XDMAC_GCFG, AT_XDMAC_GCFG_P2M);
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+ at_xdmac_write(atxdmac, AT_XDMAC_GWAC, AT_XDMAC_GWAC_P2M);
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+ }
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+}
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+
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static int at_xdmac_probe(struct platform_device *pdev)
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{
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struct at_xdmac *atxdmac;
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@@ -2147,6 +2192,8 @@ static int at_xdmac_probe(struct platfor
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dev_info(&pdev->dev, "%d channels, mapped at 0x%p\n",
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nr_channels, atxdmac->regs);
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+ at_xdmac_axi_config(pdev);
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+
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return 0;
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err_dma_unregister:
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