198 lines
6.3 KiB
Diff
198 lines
6.3 KiB
Diff
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IMPORTANT NOTE
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==============
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The content of this patch has been adapted for Linux 4.19
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Changes were made in Linux 5.x to add the bad-block limit
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to the metadata available to the driver, adding a parameter
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NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1),
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^- New bad-block limit
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This patch omits that parameter from the upstream patch
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for compatibility with the Linux 4.19 driver.
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=====
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From 049df13c4e63884fe6634db5568e08f65922256e Mon Sep 17 00:00:00 2001
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From: Jeff Kletsky <git-commits@allycomm.com>
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Date: Wed, 22 May 2019 15:05:55 -0700
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Subject: [PATCH 3/3] mtd: spinand: Add support for GigaDevice GD5F1GQ4UFxxG
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The GigaDevice GD5F1GQ4UFxxG SPI NAND is in current production devices
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and, while it has the same logical layout as the E-series devices,
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it differs in the SPI interfacing in significant ways.
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This support is contingent on previous commits to:
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* Add support for two-byte device IDs
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* Define macros for page-read ops with three-byte addresses
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http://www.gigadevice.com/datasheet/gd5f1gq4xfxxg/
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Signed-off-by: Jeff Kletsky <git-commits@allycomm.com>
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Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de>
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Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
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---
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drivers/mtd/nand/spi/gigadevice.c | 79 +++++++++++++++++++++++++------
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1 file changed, 64 insertions(+), 15 deletions(-)
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--- a/drivers/mtd/nand/spi/gigadevice.c
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+++ b/drivers/mtd/nand/spi/gigadevice.c
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@@ -9,11 +9,17 @@
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#include <linux/mtd/spinand.h>
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#define SPINAND_MFR_GIGADEVICE 0xC8
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+
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#define GD5FXGQ4XA_STATUS_ECC_1_7_BITFLIPS (1 << 4)
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#define GD5FXGQ4XA_STATUS_ECC_8_BITFLIPS (3 << 4)
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#define GD5FXGQ4UEXXG_REG_STATUS2 0xf0
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+#define GD5FXGQ4UXFXXG_STATUS_ECC_MASK (7 << 4)
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+#define GD5FXGQ4UXFXXG_STATUS_ECC_NO_BITFLIPS (0 << 4)
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+#define GD5FXGQ4UXFXXG_STATUS_ECC_1_3_BITFLIPS (1 << 4)
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+#define GD5FXGQ4UXFXXG_STATUS_ECC_UNCOR_ERROR (7 << 4)
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+
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static SPINAND_OP_VARIANTS(read_cache_variants,
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SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 2, NULL, 0),
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SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0),
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@@ -22,6 +28,14 @@ static SPINAND_OP_VARIANTS(read_cache_va
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SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0),
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SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0));
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+static SPINAND_OP_VARIANTS(read_cache_variants_f,
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+ SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 2, NULL, 0),
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+ SPINAND_PAGE_READ_FROM_CACHE_X4_OP_3A(0, 1, NULL, 0),
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+ SPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP(0, 1, NULL, 0),
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+ SPINAND_PAGE_READ_FROM_CACHE_X2_OP_3A(0, 1, NULL, 0),
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+ SPINAND_PAGE_READ_FROM_CACHE_OP_3A(true, 0, 1, NULL, 0),
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+ SPINAND_PAGE_READ_FROM_CACHE_OP_3A(false, 0, 0, NULL, 0));
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+
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static SPINAND_OP_VARIANTS(write_cache_variants,
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SPINAND_PROG_LOAD_X4(true, 0, NULL, 0),
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SPINAND_PROG_LOAD(true, 0, NULL, 0));
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@@ -59,6 +73,11 @@ static int gd5fxgq4xa_ooblayout_free(str
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return 0;
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}
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+static const struct mtd_ooblayout_ops gd5fxgq4xa_ooblayout = {
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+ .ecc = gd5fxgq4xa_ooblayout_ecc,
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+ .free = gd5fxgq4xa_ooblayout_free,
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+};
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+
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static int gd5fxgq4xa_ecc_get_status(struct spinand_device *spinand,
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u8 status)
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{
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@@ -83,7 +102,7 @@ static int gd5fxgq4xa_ecc_get_status(str
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return -EINVAL;
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}
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-static int gd5fxgq4uexxg_ooblayout_ecc(struct mtd_info *mtd, int section,
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+static int gd5fxgq4_variant2_ooblayout_ecc(struct mtd_info *mtd, int section,
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struct mtd_oob_region *region)
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{
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if (section)
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@@ -95,7 +114,7 @@ static int gd5fxgq4uexxg_ooblayout_ecc(s
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return 0;
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}
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-static int gd5fxgq4uexxg_ooblayout_free(struct mtd_info *mtd, int section,
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+static int gd5fxgq4_variant2_ooblayout_free(struct mtd_info *mtd, int section,
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struct mtd_oob_region *region)
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{
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if (section)
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@@ -108,6 +127,11 @@ static int gd5fxgq4uexxg_ooblayout_free(
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return 0;
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}
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+static const struct mtd_ooblayout_ops gd5fxgq4_variant2_ooblayout = {
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+ .ecc = gd5fxgq4_variant2_ooblayout_ecc,
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+ .free = gd5fxgq4_variant2_ooblayout_free,
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+};
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+
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static int gd5fxgq4uexxg_ecc_get_status(struct spinand_device *spinand,
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u8 status)
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{
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@@ -150,15 +174,25 @@ static int gd5fxgq4uexxg_ecc_get_status(
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return -EINVAL;
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}
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-static const struct mtd_ooblayout_ops gd5fxgq4xa_ooblayout = {
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- .ecc = gd5fxgq4xa_ooblayout_ecc,
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- .free = gd5fxgq4xa_ooblayout_free,
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-};
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+static int gd5fxgq4ufxxg_ecc_get_status(struct spinand_device *spinand,
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+ u8 status)
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+{
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+ switch (status & GD5FXGQ4UXFXXG_STATUS_ECC_MASK) {
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+ case GD5FXGQ4UXFXXG_STATUS_ECC_NO_BITFLIPS:
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+ return 0;
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-static const struct mtd_ooblayout_ops gd5fxgq4uexxg_ooblayout = {
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- .ecc = gd5fxgq4uexxg_ooblayout_ecc,
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- .free = gd5fxgq4uexxg_ooblayout_free,
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-};
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+ case GD5FXGQ4UXFXXG_STATUS_ECC_1_3_BITFLIPS:
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+ return 3;
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+
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+ case GD5FXGQ4UXFXXG_STATUS_ECC_UNCOR_ERROR:
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+ return -EBADMSG;
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+
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+ default: /* (2 << 4) through (6 << 4) are 4-8 corrected errors */
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+ return ((status & GD5FXGQ4UXFXXG_STATUS_ECC_MASK) >> 4) + 2;
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+ }
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+
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+ return -EINVAL;
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+}
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static const struct spinand_info gigadevice_spinand_table[] = {
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SPINAND_INFO("GD5F1GQ4xA", 0xF1,
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@@ -195,25 +229,40 @@ static const struct spinand_info gigadev
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&write_cache_variants,
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&update_cache_variants),
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0,
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- SPINAND_ECCINFO(&gd5fxgq4uexxg_ooblayout,
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+ SPINAND_ECCINFO(&gd5fxgq4_variant2_ooblayout,
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gd5fxgq4uexxg_ecc_get_status)),
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+ SPINAND_INFO("GD5F1GQ4UFxxG", 0xb148,
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+ NAND_MEMORG(1, 2048, 128, 64, 1024, 1, 1, 1),
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+ NAND_ECCREQ(8, 512),
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+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants_f,
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+ &write_cache_variants,
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+ &update_cache_variants),
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+ 0,
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+ SPINAND_ECCINFO(&gd5fxgq4_variant2_ooblayout,
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+ gd5fxgq4ufxxg_ecc_get_status)),
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};
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static int gigadevice_spinand_detect(struct spinand_device *spinand)
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{
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u8 *id = spinand->id.data;
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+ u16 did;
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int ret;
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/*
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- * For GD NANDs, There is an address byte needed to shift in before IDs
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- * are read out, so the first byte in raw_id is dummy.
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+ * Earlier GDF5-series devices (A,E) return [0][MID][DID]
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+ * Later (F) devices return [MID][DID1][DID2]
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*/
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- if (id[1] != SPINAND_MFR_GIGADEVICE)
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+
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+ if (id[0] == SPINAND_MFR_GIGADEVICE)
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+ did = (id[1] << 8) + id[2];
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+ else if (id[0] == 0 && id[1] == SPINAND_MFR_GIGADEVICE)
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+ did = id[2];
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+ else
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return 0;
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ret = spinand_match_and_init(spinand, gigadevice_spinand_table,
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ARRAY_SIZE(gigadevice_spinand_table),
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- id[2]);
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+ did);
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if (ret)
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return ret;
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