88 lines
2.8 KiB
Diff
88 lines
2.8 KiB
Diff
From a9f5a167be625cf0cd157aa38f3635b2b1f0cc0f Mon Sep 17 00:00:00 2001
|
|
From: Jes Sorensen <Jes.Sorensen@redhat.com>
|
|
Date: Fri, 29 Jul 2016 15:25:34 -0400
|
|
Subject: [PATCH] rtl8xxxu: Add some 8188eu registers and update
|
|
CCK0_AFE_SETTING bit defines
|
|
|
|
CCK0_AFE_SETTING is particular, it has the notion of primary RX antenna
|
|
and optional RX antenna. When configuring RX for single antenna, setup
|
|
should use the same antenna for default and optional. For AB setup,
|
|
use antenna A as default and B as optional.
|
|
|
|
In addition add info for 8188eu IOL magic interface used to send
|
|
firmware and register init files to the firmware.
|
|
|
|
Signed-off-by: Jes Sorensen <Jes.Sorensen@redhat.com>
|
|
---
|
|
.../net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h | 30 ++++++++++++++++++++--
|
|
1 file changed, 28 insertions(+), 2 deletions(-)
|
|
|
|
--- a/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h
|
|
+++ b/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h
|
|
@@ -378,6 +378,11 @@
|
|
#define PBP_PAGE_SIZE_512 0x3
|
|
#define PBP_PAGE_SIZE_1024 0x4
|
|
|
|
+/* 8188eu IOL magic */
|
|
+#define REG_PKT_BUF_ACCESS_CTRL 0x0106
|
|
+#define PKT_BUF_ACCESS_CTRL_TX 0x69
|
|
+#define PKT_BUF_ACCESS_CTRL_RX 0xa5
|
|
+
|
|
#define REG_TRXDMA_CTRL 0x010c
|
|
#define TRXDMA_CTRL_RXDMA_AGG_EN BIT(2)
|
|
#define TRXDMA_CTRL_VOQ_SHIFT 4
|
|
@@ -449,6 +454,7 @@
|
|
|
|
#define REG_FIFOPAGE 0x0204
|
|
#define REG_TDECTRL 0x0208
|
|
+
|
|
#define REG_TXDMA_OFFSET_CHK 0x020c
|
|
#define TXDMA_OFFSET_DROP_DATA_EN BIT(9)
|
|
#define REG_TXDMA_STATUS 0x0210
|
|
@@ -938,6 +944,7 @@
|
|
#define REG_FPGA1_RF_MODE 0x0900
|
|
|
|
#define REG_FPGA1_TX_INFO 0x090c
|
|
+#define REG_ANT_MAPPING1 0x0914
|
|
#define REG_DPDT_CTRL 0x092c /* 8723BU */
|
|
#define REG_RFE_CTRL_ANTA_SRC 0x0930 /* 8723BU */
|
|
#define REG_RFE_PATH_SELECT 0x0940 /* 8723BU */
|
|
@@ -949,9 +956,25 @@
|
|
|
|
#define REG_CCK0_AFE_SETTING 0x0a04
|
|
#define CCK0_AFE_RX_MASK 0x0f000000
|
|
-#define CCK0_AFE_RX_ANT_AB BIT(24)
|
|
+#define CCK0_AFE_TX_MASK 0xf0000000
|
|
#define CCK0_AFE_RX_ANT_A 0
|
|
-#define CCK0_AFE_RX_ANT_B (BIT(24) | BIT(26))
|
|
+#define CCK0_AFE_RX_ANT_B BIT(26)
|
|
+#define CCK0_AFE_RX_ANT_C BIT(27)
|
|
+#define CCK0_AFE_RX_ANT_D (BIT(26) | BIT(27))
|
|
+#define CCK0_AFE_RX_ANT_OPTION_A 0
|
|
+#define CCK0_AFE_RX_ANT_OPTION_B BIT(24)
|
|
+#define CCK0_AFE_RX_ANT_OPTION_C BIT(25)
|
|
+#define CCK0_AFE_RX_ANT_OPTION_D (BIT(24) | BIT(25))
|
|
+#define CCK0_AFE_TX_ANT_A BIT(31)
|
|
+#define CCK0_AFE_TX_ANT_B BIT(30)
|
|
+
|
|
+#define REG_CCK_ANTDIV_PARA2 0x0a04
|
|
+#define REG_BB_POWER_SAVE4 0x0a74
|
|
+
|
|
+/* 8188eu */
|
|
+#define REG_LNA_SWITCH 0x0b2c
|
|
+#define LNA_SWITCH_DISABLE_CSCG BIT(22)
|
|
+#define LNA_SWITCH_OUTPUT_CG BIT(31)
|
|
|
|
#define REG_CONFIG_ANT_A 0x0b68
|
|
#define REG_CONFIG_ANT_B 0x0b6c
|
|
@@ -1004,6 +1027,9 @@
|
|
|
|
#define REG_OFDM0_RX_IQ_EXT_ANTA 0x0ca0
|
|
|
|
+/* 8188eu */
|
|
+#define REG_ANTDIV_PARA1 0x0ca4
|
|
+
|
|
/* 8723bu */
|
|
#define REG_OFDM0_TX_PSDO_NOISE_WEIGHT 0x0ce4
|
|
|