132 lines
4.0 KiB
Diff
132 lines
4.0 KiB
Diff
From 73b7a6047971aa6ce4a70fc4901964d14f077171 Mon Sep 17 00:00:00 2001
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From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
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Date: Wed, 6 Jan 2021 22:32:02 +0100
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Subject: [PATCH] net: dsa: bcm_sf2: support BCM4908's integrated switch
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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BCM4908 family SoCs come with integrated Starfighter 2 switch. Its
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registers layout it a mix of BCM7278 and BCM7445. It has 5 integrated
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PHYs and 8 ports. It also supports RGMII and SerDes.
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Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
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Acked-by: Florian Fainelli <f.fainelli@gmail.com>
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Link: https://lore.kernel.org/r/20210106213202.17459-3-zajec5@gmail.com
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Signed-off-by: Jakub Kicinski <kuba@kernel.org>
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---
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drivers/net/dsa/b53/b53_common.c | 14 +++++++++++++
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drivers/net/dsa/b53/b53_priv.h | 1 +
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drivers/net/dsa/bcm_sf2.c | 36 +++++++++++++++++++++++++++++---
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drivers/net/dsa/bcm_sf2_regs.h | 1 +
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4 files changed, 49 insertions(+), 3 deletions(-)
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--- a/drivers/net/dsa/b53/b53_common.c
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+++ b/drivers/net/dsa/b53/b53_common.c
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@@ -2271,6 +2271,22 @@ static const struct b53_chip_data b53_sw
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.jumbo_pm_reg = B53_JUMBO_PORT_MASK,
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.jumbo_size_reg = B53_JUMBO_MAX_SIZE,
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},
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+ /* Starfighter 2 */
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+ {
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+ .chip_id = BCM4908_DEVICE_ID,
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+ .dev_name = "BCM4908",
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+ .vlans = 4096,
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+ .enabled_ports = 0x1bf,
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+#if 0
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+ .arl_bins = 4,
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+ .arl_buckets = 256,
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+#endif
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+ .cpu_port = 8, /* TODO: ports 4, 5, 8 */
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+ .vta_regs = B53_VTA_REGS,
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+ .duplex_reg = B53_DUPLEX_STAT_GE,
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+ .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
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+ .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
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+ },
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{
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.chip_id = BCM7445_DEVICE_ID,
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.dev_name = "BCM7445",
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--- a/drivers/net/dsa/b53/b53_priv.h
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+++ b/drivers/net/dsa/b53/b53_priv.h
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@@ -64,6 +64,7 @@ struct b53_io_ops {
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#define B53_INVALID_LANE 0xff
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enum {
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+ BCM4908_DEVICE_ID = 0x4908,
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BCM5325_DEVICE_ID = 0x25,
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BCM5365_DEVICE_ID = 0x65,
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BCM5389_DEVICE_ID = 0x89,
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--- a/drivers/net/dsa/bcm_sf2.c
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+++ b/drivers/net/dsa/bcm_sf2.c
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@@ -61,7 +61,8 @@ static void bcm_sf2_imp_setup(struct dsa
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b53_brcm_hdr_setup(ds, port);
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if (port == 8) {
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- if (priv->type == BCM7445_DEVICE_ID)
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+ if (priv->type == BCM4908_DEVICE_ID ||
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+ priv->type == BCM7445_DEVICE_ID)
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offset = CORE_STS_OVERRIDE_IMP;
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else
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offset = CORE_STS_OVERRIDE_IMP2;
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@@ -543,7 +544,8 @@ static void bcm_sf2_sw_mac_config(struct
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if (port == core_readl(priv, CORE_IMP0_PRT_ID))
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return;
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- if (priv->type == BCM7445_DEVICE_ID)
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+ if (priv->type == BCM4908_DEVICE_ID ||
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+ priv->type == BCM7445_DEVICE_ID)
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offset = CORE_STS_OVERRIDE_GMIIP_PORT(port);
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else
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offset = CORE_STS_OVERRIDE_GMIIP2_PORT(port);
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@@ -990,6 +992,30 @@ struct bcm_sf2_of_data {
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unsigned int num_cfp_rules;
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};
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+static const u16 bcm_sf2_4908_reg_offsets[] = {
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+ [REG_SWITCH_CNTRL] = 0x00,
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+ [REG_SWITCH_STATUS] = 0x04,
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+ [REG_DIR_DATA_WRITE] = 0x08,
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+ [REG_DIR_DATA_READ] = 0x0c,
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+ [REG_SWITCH_REVISION] = 0x10,
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+ [REG_PHY_REVISION] = 0x14,
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+ [REG_SPHY_CNTRL] = 0x24,
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+ [REG_CROSSBAR] = 0xc8,
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+ [REG_RGMII_0_CNTRL] = 0xe0,
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+ [REG_RGMII_1_CNTRL] = 0xec,
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+ [REG_RGMII_2_CNTRL] = 0xf8,
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+ [REG_LED_0_CNTRL] = 0x40,
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+ [REG_LED_1_CNTRL] = 0x4c,
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+ [REG_LED_2_CNTRL] = 0x58,
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+};
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+
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+static const struct bcm_sf2_of_data bcm_sf2_4908_data = {
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+ .type = BCM4908_DEVICE_ID,
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+ .core_reg_align = 0,
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+ .reg_offsets = bcm_sf2_4908_reg_offsets,
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+ .num_cfp_rules = 0, /* FIXME */
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+};
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+
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/* Register offsets for the SWITCH_REG_* block */
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static const u16 bcm_sf2_7445_reg_offsets[] = {
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[REG_SWITCH_CNTRL] = 0x00,
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@@ -1038,6 +1064,9 @@ static const struct bcm_sf2_of_data bcm_
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};
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static const struct of_device_id bcm_sf2_of_match[] = {
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+ { .compatible = "brcm,bcm4908-switch",
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+ .data = &bcm_sf2_4908_data
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+ },
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{ .compatible = "brcm,bcm7445-switch-v4.0",
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.data = &bcm_sf2_7445_data
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},
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--- a/drivers/net/dsa/bcm_sf2_regs.h
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+++ b/drivers/net/dsa/bcm_sf2_regs.h
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@@ -17,6 +17,7 @@ enum bcm_sf2_reg_offs {
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REG_SWITCH_REVISION,
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REG_PHY_REVISION,
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REG_SPHY_CNTRL,
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+ REG_CROSSBAR,
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REG_RGMII_0_CNTRL,
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REG_RGMII_1_CNTRL,
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REG_RGMII_2_CNTRL,
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