71 lines
2.5 KiB
Diff
71 lines
2.5 KiB
Diff
From 287fbc1b38d530aef3bc66420db7591808ff9969 Mon Sep 17 00:00:00 2001
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From: Phil Elwell <phil@raspberrypi.com>
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Date: Wed, 13 May 2020 20:10:15 +0100
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Subject: [PATCH] sc16is7xx: Fix for hardware flow control
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The SC16IS7XX hardware flow control is mishandled by the driver in
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a number of ways:
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1. The set_baud method accidentally clears it when setting EFR bit.
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2. Even though hardware flow control is enabled, it isn't indicated
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back to the serial framework.
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3. Applying the flow control clears the EFR bit.
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4. The CTS support is not indicated in the return from
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sc16is7xx_get_mctrl.
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Address all of those issues using a mixture of patches found on the
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linked pages.
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See: https://github.com/raspberrypi/linux/issues/2542
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See: https://www.spinics.net/lists/linux-serial/msg21794.html
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Signed-off-by: Phil Elwell <phil@raspberrypi.com>
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---
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drivers/tty/serial/sc16is7xx.c | 14 ++++++++++----
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1 file changed, 10 insertions(+), 4 deletions(-)
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--- a/drivers/tty/serial/sc16is7xx.c
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+++ b/drivers/tty/serial/sc16is7xx.c
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@@ -525,8 +525,9 @@ static int sc16is7xx_set_baud(struct uar
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/* Enable enhanced features */
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regcache_cache_bypass(s->regmap, true);
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- sc16is7xx_port_write(port, SC16IS7XX_EFR_REG,
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- SC16IS7XX_EFR_ENABLE_BIT);
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+ sc16is7xx_port_update(port, SC16IS7XX_EFR_REG,
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+ SC16IS7XX_EFR_ENABLE_BIT,
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+ SC16IS7XX_EFR_ENABLE_BIT);
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regcache_cache_bypass(s->regmap, false);
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/* Put LCR back to the normal mode */
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@@ -856,7 +857,7 @@ static unsigned int sc16is7xx_get_mctrl(
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/* DCD and DSR are not wired and CTS/RTS is handled automatically
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* so just indicate DSR and CAR asserted
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*/
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- return TIOCM_DSR | TIOCM_CAR;
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+ return TIOCM_DSR | TIOCM_CAR | TIOCM_RI | TIOCM_CTS;
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}
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static void sc16is7xx_set_mctrl(struct uart_port *port, unsigned int mctrl)
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@@ -943,14 +944,19 @@ static void sc16is7xx_set_termios(struct
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regcache_cache_bypass(s->regmap, true);
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sc16is7xx_port_write(port, SC16IS7XX_XON1_REG, termios->c_cc[VSTART]);
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sc16is7xx_port_write(port, SC16IS7XX_XOFF1_REG, termios->c_cc[VSTOP]);
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- if (termios->c_cflag & CRTSCTS)
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+ if (termios->c_cflag & CRTSCTS) {
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flow |= SC16IS7XX_EFR_AUTOCTS_BIT |
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SC16IS7XX_EFR_AUTORTS_BIT;
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+ port->status |= UPSTAT_AUTOCTS;
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+ };
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if (termios->c_iflag & IXON)
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flow |= SC16IS7XX_EFR_SWFLOW3_BIT;
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if (termios->c_iflag & IXOFF)
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flow |= SC16IS7XX_EFR_SWFLOW1_BIT;
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+ /* Always set enable enhanced */
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+ flow |= SC16IS7XX_EFR_ENABLE_BIT;
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+
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sc16is7xx_port_write(port, SC16IS7XX_EFR_REG, flow);
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regcache_cache_bypass(s->regmap, false);
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