41 lines
1.6 KiB
Diff
41 lines
1.6 KiB
Diff
From 43f3f187e6f62ca40802afe39495c8a3e20b4bfa Mon Sep 17 00:00:00 2001
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From: =?UTF-8?q?Pali=20Roh=C3=A1r?= <pali@kernel.org>
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Date: Mon, 10 Jan 2022 01:50:50 +0100
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Subject: [PATCH] PCI: aardvark: Replace custom PCIE_CORE_INT_* macros with
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PCI_INTERRUPT_*
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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Header file linux/pci.h defines enum pci_interrupt_pin with corresponding
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PCI_INTERRUPT_* values.
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Signed-off-by: Pali Rohár <pali@kernel.org>
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Signed-off-by: Marek Behún <kabel@kernel.org>
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---
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drivers/pci/controller/pci-aardvark.c | 6 +-----
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1 file changed, 1 insertion(+), 5 deletions(-)
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--- a/drivers/pci/controller/pci-aardvark.c
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+++ b/drivers/pci/controller/pci-aardvark.c
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@@ -38,10 +38,6 @@
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#define PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX_EN BIT(6)
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#define PCIE_CORE_ERR_CAPCTL_ECRC_CHCK BIT(7)
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#define PCIE_CORE_ERR_CAPCTL_ECRC_CHCK_RCV BIT(8)
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-#define PCIE_CORE_INT_A_ASSERT_ENABLE 1
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-#define PCIE_CORE_INT_B_ASSERT_ENABLE 2
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-#define PCIE_CORE_INT_C_ASSERT_ENABLE 3
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-#define PCIE_CORE_INT_D_ASSERT_ENABLE 4
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/* PIO registers base address and register offsets */
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#define PIO_BASE_ADDR 0x4000
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#define PIO_CTRL (PIO_BASE_ADDR + 0x0)
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@@ -961,7 +957,7 @@ static int advk_sw_pci_bridge_init(struc
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bridge->conf.pref_mem_limit = cpu_to_le16(PCI_PREF_RANGE_TYPE_64);
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/* Support interrupt A for MSI feature */
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- bridge->conf.intpin = PCIE_CORE_INT_A_ASSERT_ENABLE;
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+ bridge->conf.intpin = PCI_INTERRUPT_INTA;
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/* Aardvark HW provides PCIe Capability structure in version 2 */
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bridge->pcie_conf.cap = cpu_to_le16(2);
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