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Qualcomm Atheros IPQ807x is a modern WiSoC featuring: * Quad Core ARMv8 Cortex A-53 * @ 2.2 GHz (IPQ8072A/4A/6A/8A) Codename Hawkeye * @ 1.4 GHz (IPQ8070A/1A) Codename Acorn * Dual Band simultaneaous IEEE 802.11ax * 5G: 8x8/80 or 4x4/160MHz (IPQ8074A/8A) * 5G: 4x4/80 or 2x2/160MHz (IPQ8071A/2A/6A) * 5G: 2x2/80MHz (IPQ8070A) * 2G: 4x4/40MHz (IPQ8072A/4A/6A/8A) * 2G: 2x2/40MHz (IPQ8070A/1A) * 1x PSGMII via QCA8072/5 (Max 5x 1GbE ports) * 2x SGMII/USXGMII (1/2.5/5/10 GbE) on Hawkeye * 2x SGMII/USXGMII (1/2.5/5 GbE) on Acorn * DDR3L/4 32/16 bit up to 2400MT/s * SDIO 3.0/SD card 3.0/eMMC 5.1 * Dual USB 3.0 * One PCIe Gen2.1 and one PCIe Gen3.0 port (Single lane) * Parallel NAND (ONFI)/LCD * 6x QUP BLSP SPI/I2C/UART * I2S, PCM, and TDMA * HW PWM * 1.8V configurable GPIO * Companion PMP8074 PMIC via SPMI (GPIOS, RTC etc) Note that only v2 SOC models aka the ones ending with A suffix are supported, v1 models do not comply to the final 802.11ax and have lower clocks, lack the Gen3 PCIe etc. SoC itself has two UBI32 cores for the NSS offloading system, however currently no offloading is supported. Signed-off-by: Robert Marko <robimarko@gmail.com>
37 lines
1.3 KiB
Diff
37 lines
1.3 KiB
Diff
From ee9002a825695b5dca76f758a9365ca7f7d18265 Mon Sep 17 00:00:00 2001
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From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
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Date: Wed, 4 May 2022 15:19:16 +0200
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Subject: [PATCH] arm64: dts: qcom: correct DWC3 node names and unit addresses
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Align DWC3 USB node names with DT schema ("usb" is expected) and correct
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the unit addresses to match the "reg" property. This also implies
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overriding nodes by label, instead of full path.
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Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
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Link: https://lore.kernel.org/r/20220504131923.214367-7-krzysztof.kozlowski@linaro.org
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Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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---
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arch/arm64/boot/dts/qcom/ipq8074.dtsi | 4 ++--
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1 file changed, 2 insertions(+), 2 deletions(-)
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--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
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+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
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@@ -578,7 +578,7 @@
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resets = <&gcc GCC_USB0_BCR>;
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status = "disabled";
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- dwc_0: dwc3@8a00000 {
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+ dwc_0: usb@8a00000 {
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compatible = "snps,dwc3";
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reg = <0x8a00000 0xcd00>;
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interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
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@@ -618,7 +618,7 @@
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resets = <&gcc GCC_USB1_BCR>;
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status = "disabled";
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- dwc_1: dwc3@8c00000 {
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+ dwc_1: usb@8c00000 {
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compatible = "snps,dwc3";
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reg = <0x8c00000 0xcd00>;
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interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
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