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Qualcomm Atheros IPQ807x is a modern WiSoC featuring: * Quad Core ARMv8 Cortex A-53 * @ 2.2 GHz (IPQ8072A/4A/6A/8A) Codename Hawkeye * @ 1.4 GHz (IPQ8070A/1A) Codename Acorn * Dual Band simultaneaous IEEE 802.11ax * 5G: 8x8/80 or 4x4/160MHz (IPQ8074A/8A) * 5G: 4x4/80 or 2x2/160MHz (IPQ8071A/2A/6A) * 5G: 2x2/80MHz (IPQ8070A) * 2G: 4x4/40MHz (IPQ8072A/4A/6A/8A) * 2G: 2x2/40MHz (IPQ8070A/1A) * 1x PSGMII via QCA8072/5 (Max 5x 1GbE ports) * 2x SGMII/USXGMII (1/2.5/5/10 GbE) on Hawkeye * 2x SGMII/USXGMII (1/2.5/5 GbE) on Acorn * DDR3L/4 32/16 bit up to 2400MT/s * SDIO 3.0/SD card 3.0/eMMC 5.1 * Dual USB 3.0 * One PCIe Gen2.1 and one PCIe Gen3.0 port (Single lane) * Parallel NAND (ONFI)/LCD * 6x QUP BLSP SPI/I2C/UART * I2S, PCM, and TDMA * HW PWM * 1.8V configurable GPIO * Companion PMP8074 PMIC via SPMI (GPIOS, RTC etc) Note that only v2 SOC models aka the ones ending with A suffix are supported, v1 models do not comply to the final 802.11ax and have lower clocks, lack the Gen3 PCIe etc. SoC itself has two UBI32 cores for the NSS offloading system, however currently no offloading is supported. Signed-off-by: Robert Marko <robimarko@gmail.com>
54 lines
1.8 KiB
Diff
54 lines
1.8 KiB
Diff
From 1a82d7080001d395563ad8266d120d4cf63ad0a5 Mon Sep 17 00:00:00 2001
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From: Shawn Guo <shawn.guo@linaro.org>
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Date: Wed, 29 Sep 2021 11:42:46 +0800
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Subject: [PATCH] arm64: dts: qcom: msm8996: Move '#clock-cells' to QMP PHY
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child node
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'#clock-cells' is a required property of QMP PHY child node, not itself.
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Move it to fix the dtbs_check warnings.
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There are only '#clock-cells' removal from SM8350 QMP PHY nodes, because
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child nodes already have the property.
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Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
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Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
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Link: https://lore.kernel.org/r/20210929034253.24570-4-shawn.guo@linaro.org
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---
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arch/arm64/boot/dts/qcom/ipq8074.dtsi | 4 ++--
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1 file changed, 2 insertions(+), 2 deletions(-)
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--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
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+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
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@@ -91,7 +91,6 @@
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ssphy_1: phy@58000 {
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compatible = "qcom,ipq8074-qmp-usb3-phy";
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reg = <0x00058000 0x1c4>;
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- #clock-cells = <1>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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@@ -112,6 +111,7 @@
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<0x00058800 0x1f8>, /* PCS */
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<0x00058600 0x044>; /* PCS misc*/
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#phy-cells = <0>;
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+ #clock-cells = <1>;
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clocks = <&gcc GCC_USB1_PIPE_CLK>;
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clock-names = "pipe0";
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clock-output-names = "gcc_usb1_pipe_clk_src";
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@@ -134,7 +134,6 @@
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ssphy_0: phy@78000 {
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compatible = "qcom,ipq8074-qmp-usb3-phy";
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reg = <0x00078000 0x1c4>;
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- #clock-cells = <1>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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@@ -155,6 +154,7 @@
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<0x00078800 0x1f8>, /* PCS */
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<0x00078600 0x044>; /* PCS misc*/
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#phy-cells = <0>;
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+ #clock-cells = <1>;
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clocks = <&gcc GCC_USB0_PIPE_CLK>;
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clock-names = "pipe0";
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clock-output-names = "gcc_usb0_pipe_clk_src";
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