154 lines
5.1 KiB
Diff
154 lines
5.1 KiB
Diff
From 23680321789863bab2d60af507858ce50ff9f56a Mon Sep 17 00:00:00 2001
|
|
From: =?UTF-8?q?Alexis=20Lothor=C3=A9?= <alexis.lothore@bootlin.com>
|
|
Date: Mon, 29 May 2023 10:02:46 +0200
|
|
Subject: [PATCH 6/6] net: dsa: mv88e6xxx: enable support for 88E6361 switch
|
|
MIME-Version: 1.0
|
|
Content-Type: text/plain; charset=UTF-8
|
|
Content-Transfer-Encoding: 8bit
|
|
|
|
Marvell 88E6361 is an 8-port switch derived from the
|
|
88E6393X/88E9193X/88E6191X switches family. It can benefit from the
|
|
existing mv88e6xxx driver by simply adding the proper switch description in
|
|
the driver. Main differences with other switches from this
|
|
family are:
|
|
- 8 ports exposed (instead of 11): ports 1, 2 and 8 not available
|
|
- No 5GBase-x nor SFI/USXGMII support
|
|
|
|
Signed-off-by: Alexis Lothoré <alexis.lothore@bootlin.com>
|
|
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
|
|
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
|
|
---
|
|
drivers/net/dsa/mv88e6xxx/chip.c | 42 ++++++++++++++++++++++++++++----
|
|
drivers/net/dsa/mv88e6xxx/chip.h | 3 ++-
|
|
drivers/net/dsa/mv88e6xxx/port.c | 14 ++++++++---
|
|
drivers/net/dsa/mv88e6xxx/port.h | 1 +
|
|
4 files changed, 51 insertions(+), 9 deletions(-)
|
|
|
|
--- a/drivers/net/dsa/mv88e6xxx/chip.c
|
|
+++ b/drivers/net/dsa/mv88e6xxx/chip.c
|
|
@@ -797,6 +797,8 @@ static void mv88e6393x_phylink_get_caps(
|
|
unsigned long *supported = config->supported_interfaces;
|
|
bool is_6191x =
|
|
chip->info->prod_num == MV88E6XXX_PORT_SWITCH_ID_PROD_6191X;
|
|
+ bool is_6361 =
|
|
+ chip->info->prod_num == MV88E6XXX_PORT_SWITCH_ID_PROD_6361;
|
|
|
|
mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported);
|
|
|
|
@@ -811,13 +813,17 @@ static void mv88e6393x_phylink_get_caps(
|
|
/* 6191X supports >1G modes only on port 10 */
|
|
if (!is_6191x || port == 10) {
|
|
__set_bit(PHY_INTERFACE_MODE_2500BASEX, supported);
|
|
- __set_bit(PHY_INTERFACE_MODE_5GBASER, supported);
|
|
- __set_bit(PHY_INTERFACE_MODE_10GBASER, supported);
|
|
+ config->mac_capabilities |= MAC_2500FD;
|
|
+
|
|
+ /* 6361 only supports up to 2500BaseX */
|
|
+ if (!is_6361) {
|
|
+ __set_bit(PHY_INTERFACE_MODE_5GBASER, supported);
|
|
+ __set_bit(PHY_INTERFACE_MODE_10GBASER, supported);
|
|
+ config->mac_capabilities |= MAC_5000FD |
|
|
+ MAC_10000FD;
|
|
+ }
|
|
/* FIXME: USXGMII is not supported yet */
|
|
/* __set_bit(PHY_INTERFACE_MODE_USXGMII, supported); */
|
|
-
|
|
- config->mac_capabilities |= MAC_2500FD | MAC_5000FD |
|
|
- MAC_10000FD;
|
|
}
|
|
}
|
|
|
|
@@ -6231,6 +6237,32 @@ static const struct mv88e6xxx_info mv88e
|
|
.ptp_support = true,
|
|
.ops = &mv88e6352_ops,
|
|
},
|
|
+ [MV88E6361] = {
|
|
+ .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6361,
|
|
+ .family = MV88E6XXX_FAMILY_6393,
|
|
+ .name = "Marvell 88E6361",
|
|
+ .num_databases = 4096,
|
|
+ .num_macs = 16384,
|
|
+ .num_ports = 11,
|
|
+ /* Ports 1, 2 and 8 are not routed */
|
|
+ .invalid_port_mask = BIT(1) | BIT(2) | BIT(8),
|
|
+ .num_internal_phys = 5,
|
|
+ .internal_phys_offset = 3,
|
|
+ .max_vid = 4095,
|
|
+ .max_sid = 63,
|
|
+ .port_base_addr = 0x0,
|
|
+ .phy_base_addr = 0x0,
|
|
+ .global1_addr = 0x1b,
|
|
+ .global2_addr = 0x1c,
|
|
+ .age_time_coeff = 3750,
|
|
+ .g1_irqs = 10,
|
|
+ .g2_irqs = 14,
|
|
+ .atu_move_port_mask = 0x1f,
|
|
+ .pvt = true,
|
|
+ .multi_chip = true,
|
|
+ .ptp_support = true,
|
|
+ .ops = &mv88e6393x_ops,
|
|
+ },
|
|
[MV88E6390] = {
|
|
.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390,
|
|
.family = MV88E6XXX_FAMILY_6390,
|
|
--- a/drivers/net/dsa/mv88e6xxx/chip.h
|
|
+++ b/drivers/net/dsa/mv88e6xxx/chip.h
|
|
@@ -82,6 +82,7 @@ enum mv88e6xxx_model {
|
|
MV88E6350,
|
|
MV88E6351,
|
|
MV88E6352,
|
|
+ MV88E6361,
|
|
MV88E6390,
|
|
MV88E6390X,
|
|
MV88E6393X,
|
|
@@ -100,7 +101,7 @@ enum mv88e6xxx_family {
|
|
MV88E6XXX_FAMILY_6351, /* 6171 6175 6350 6351 */
|
|
MV88E6XXX_FAMILY_6352, /* 6172 6176 6240 6352 */
|
|
MV88E6XXX_FAMILY_6390, /* 6190 6190X 6191 6290 6390 6390X */
|
|
- MV88E6XXX_FAMILY_6393, /* 6191X 6193X 6393X */
|
|
+ MV88E6XXX_FAMILY_6393, /* 6191X 6193X 6361 6393X */
|
|
};
|
|
|
|
/**
|
|
--- a/drivers/net/dsa/mv88e6xxx/port.c
|
|
+++ b/drivers/net/dsa/mv88e6xxx/port.c
|
|
@@ -424,6 +424,10 @@ int mv88e6393x_port_set_speed_duplex(str
|
|
u16 reg, ctrl;
|
|
int err;
|
|
|
|
+ if (chip->info->prod_num == MV88E6XXX_PORT_SWITCH_ID_PROD_6361 &&
|
|
+ speed > 2500)
|
|
+ return -EOPNOTSUPP;
|
|
+
|
|
if (speed == 200 && port != 0)
|
|
return -EOPNOTSUPP;
|
|
|
|
@@ -506,10 +510,14 @@ int mv88e6393x_port_set_speed_duplex(str
|
|
phy_interface_t mv88e6393x_port_max_speed_mode(struct mv88e6xxx_chip *chip,
|
|
int port)
|
|
{
|
|
- if (port == 0 || port == 9 || port == 10)
|
|
- return PHY_INTERFACE_MODE_10GBASER;
|
|
|
|
- return PHY_INTERFACE_MODE_NA;
|
|
+ if (port != 0 && port != 9 && port != 10)
|
|
+ return PHY_INTERFACE_MODE_NA;
|
|
+
|
|
+ if (chip->info->prod_num == MV88E6XXX_PORT_SWITCH_ID_PROD_6361)
|
|
+ return PHY_INTERFACE_MODE_2500BASEX;
|
|
+
|
|
+ return PHY_INTERFACE_MODE_10GBASER;
|
|
}
|
|
|
|
static int mv88e6xxx_port_set_cmode(struct mv88e6xxx_chip *chip, int port,
|
|
--- a/drivers/net/dsa/mv88e6xxx/port.h
|
|
+++ b/drivers/net/dsa/mv88e6xxx/port.h
|
|
@@ -133,6 +133,7 @@
|
|
#define MV88E6XXX_PORT_SWITCH_ID_PROD_6220 0x2200
|
|
#define MV88E6XXX_PORT_SWITCH_ID_PROD_6240 0x2400
|
|
#define MV88E6XXX_PORT_SWITCH_ID_PROD_6250 0x2500
|
|
+#define MV88E6XXX_PORT_SWITCH_ID_PROD_6361 0x2610
|
|
#define MV88E6XXX_PORT_SWITCH_ID_PROD_6290 0x2900
|
|
#define MV88E6XXX_PORT_SWITCH_ID_PROD_6321 0x3100
|
|
#define MV88E6XXX_PORT_SWITCH_ID_PROD_6141 0x3400
|