79 lines
2.6 KiB
Diff
79 lines
2.6 KiB
Diff
From d2a60430df21f213b9b9d2eb46d2f4afbbea3213 Mon Sep 17 00:00:00 2001
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From: Maxime Ripard <maxime@cerno.tech>
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Date: Fri, 4 Mar 2022 16:24:00 +0100
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Subject: [PATCH] drm/vc4: hvs: Reset muxes at probe time
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By default, the HVS driver will force the HVS output 3 to be muxed to
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the HVS channel 2. However, the Transposer can only be assigned to the
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HVS channel 2, so whenever we try to use the writeback connector, we'll
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mux its associated output (Output 2) to the channel 2.
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This leads to both the output 2 and 3 feeding from the same channel,
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which is explicitly discouraged in the documentation.
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In order to avoid this, let's reset all the output muxes to their reset
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value.
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Fixes: 87ebcd42fb7b ("drm/vc4: crtc: Assign output to channel automatically")
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Signed-off-by: Maxime Ripard <maxime@cerno.tech>
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---
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drivers/gpu/drm/vc4/vc4_hvs.c | 26 +++++++++++++++++++++-----
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1 file changed, 21 insertions(+), 5 deletions(-)
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--- a/drivers/gpu/drm/vc4/vc4_hvs.c
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+++ b/drivers/gpu/drm/vc4/vc4_hvs.c
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@@ -1017,6 +1017,7 @@ static int vc4_hvs_bind(struct device *d
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struct vc4_hvs *hvs = NULL;
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int ret;
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u32 dispctrl;
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+ u32 reg;
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hvs = devm_kzalloc(&pdev->dev, sizeof(*hvs), GFP_KERNEL);
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if (!hvs)
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@@ -1090,6 +1091,26 @@ static int vc4_hvs_bind(struct device *d
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vc4->hvs = hvs;
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+ reg = HVS_READ(SCALER_DISPECTRL);
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+ reg &= ~SCALER_DISPECTRL_DSP2_MUX_MASK;
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+ HVS_WRITE(SCALER_DISPECTRL,
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+ reg | VC4_SET_FIELD(0, SCALER_DISPECTRL_DSP2_MUX));
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+
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+ reg = HVS_READ(SCALER_DISPCTRL);
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+ reg &= ~SCALER_DISPCTRL_DSP3_MUX_MASK;
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+ HVS_WRITE(SCALER_DISPCTRL,
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+ reg | VC4_SET_FIELD(3, SCALER_DISPCTRL_DSP3_MUX));
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+
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+ reg = HVS_READ(SCALER_DISPEOLN);
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+ reg &= ~SCALER_DISPEOLN_DSP4_MUX_MASK;
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+ HVS_WRITE(SCALER_DISPEOLN,
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+ reg | VC4_SET_FIELD(3, SCALER_DISPEOLN_DSP4_MUX));
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+
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+ reg = HVS_READ(SCALER_DISPDITHER);
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+ reg &= ~SCALER_DISPDITHER_DSP5_MUX_MASK;
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+ HVS_WRITE(SCALER_DISPDITHER,
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+ reg | VC4_SET_FIELD(3, SCALER_DISPDITHER_DSP5_MUX));
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+
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dispctrl = HVS_READ(SCALER_DISPCTRL);
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dispctrl |= SCALER_DISPCTRL_ENABLE;
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@@ -1097,10 +1118,6 @@ static int vc4_hvs_bind(struct device *d
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SCALER_DISPCTRL_DISPEIRQ(1) |
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SCALER_DISPCTRL_DISPEIRQ(2);
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- /* Set DSP3 (PV1) to use HVS channel 2, which would otherwise
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- * be unused.
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- */
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- dispctrl &= ~SCALER_DISPCTRL_DSP3_MUX_MASK;
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dispctrl &= ~(SCALER_DISPCTRL_DMAEIRQ |
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SCALER_DISPCTRL_SLVWREIRQ |
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SCALER_DISPCTRL_SLVRDEIRQ |
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@@ -1114,7 +1131,6 @@ static int vc4_hvs_bind(struct device *d
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SCALER_DISPCTRL_DSPEISLUR(1) |
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SCALER_DISPCTRL_DSPEISLUR(2) |
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SCALER_DISPCTRL_SCLEIRQ);
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- dispctrl |= VC4_SET_FIELD(2, SCALER_DISPCTRL_DSP3_MUX);
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HVS_WRITE(SCALER_DISPCTRL, dispctrl);
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