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a9b6077402
* Refreshed patches Compile-tested: ar71xx, ramips/mt7621, x86/64 Run-tested: ar71xx Signed-off-by: Stijn Segers <foss@volatilesystems.org>
28 lines
1.0 KiB
Diff
28 lines
1.0 KiB
Diff
From bf239659e82c137de23c322fa852b24a0acd3156 Mon Sep 17 00:00:00 2001
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From: Eric Anholt <eric@anholt.net>
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Date: Thu, 31 Mar 2016 12:51:04 -0700
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Subject: [PATCH] clk: bcm2835: Don't rate change PLLs on behalf of dividers.
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Our core PLLs are intended to be configured once and left alone. With
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the flag set, asking to set the PLLD_DSI1 clock rate would change PLLD
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just to get closer to the requested DSI clock, thus changing PLLD_PER,
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the UART and ethernet PHY clock rates downstream of it, and breaking
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ethernet.
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Signed-off-by: Eric Anholt <eric@anholt.net>
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---
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drivers/clk/bcm/clk-bcm2835.c | 2 +-
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1 file changed, 1 insertion(+), 1 deletion(-)
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--- a/drivers/clk/bcm/clk-bcm2835.c
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+++ b/drivers/clk/bcm/clk-bcm2835.c
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@@ -1215,7 +1215,7 @@ bcm2835_register_pll_divider(struct bcm2
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init.num_parents = 1;
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init.name = divider_name;
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init.ops = &bcm2835_pll_divider_clk_ops;
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- init.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED;
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+ init.flags = CLK_IGNORE_UNUSED;
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divider = devm_kzalloc(cprman->dev, sizeof(*divider), GFP_KERNEL);
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if (!divider)
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