134 lines
5.9 KiB
Diff
134 lines
5.9 KiB
Diff
From 86c0c154a759f2af9612a04bdf29110f02dce956 Mon Sep 17 00:00:00 2001
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From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <arinc.unal@arinc9.com>
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Date: Thu, 14 Mar 2024 12:33:42 +0300
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Subject: [PATCH 3/3] net: dsa: mt7530: fix handling of all link-local frames
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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[ Upstream commit 69ddba9d170bdaee1dc0eb4ced38d7e4bb7b92af ]
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Currently, the MT753X switches treat frames with :01-0D and :0F MAC DAs as
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regular multicast frames, therefore flooding them to user ports.
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On page 205, section "8.6.3 Frame filtering" of the active standard, IEEE
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Std 802.1Q™-2022, it is stated that frames with 01:80:C2:00:00:00-0F as MAC
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DA must only be propagated to C-VLAN and MAC Bridge components. That means
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VLAN-aware and VLAN-unaware bridges. On the switch designs with CPU ports,
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these frames are supposed to be processed by the CPU (software). So we make
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the switch only forward them to the CPU port. And if received from a CPU
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port, forward to a single port. The software is responsible of making the
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switch conform to the latter by setting a single port as destination port
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on the special tag.
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This switch intellectual property cannot conform to this part of the
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standard fully. Whilst the REV_UN frame tag covers the remaining :04-0D and
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:0F MAC DAs, it also includes :22-FF which the scope of propagation is not
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supposed to be restricted for these MAC DAs.
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Set frames with :01-03 MAC DAs to be trapped to the CPU port(s). Add a
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comment for the remaining MAC DAs.
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Note that the ingress port must have a PVID assigned to it for the switch
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to forward untagged frames. A PVID is set by default on VLAN-aware and
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VLAN-unaware ports. However, when the network interface that pertains to
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the ingress port is attached to a vlan_filtering enabled bridge, the user
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can remove the PVID assignment from it which would prevent the link-local
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frames from being trapped to the CPU port. I am yet to see a way to forward
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link-local frames while preventing other untagged frames from being
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forwarded too.
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Fixes: b8f126a8d543 ("net-next: dsa: add dsa support for Mediatek MT7530 switch")
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Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
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Signed-off-by: Paolo Abeni <pabeni@redhat.com>
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Signed-off-by: Sasha Levin <sashal@kernel.org>
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---
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drivers/net/dsa/mt7530.c | 37 +++++++++++++++++++++++++++++++++----
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drivers/net/dsa/mt7530.h | 13 +++++++++++++
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2 files changed, 46 insertions(+), 4 deletions(-)
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--- a/drivers/net/dsa/mt7530.c
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+++ b/drivers/net/dsa/mt7530.c
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@@ -998,6 +998,21 @@ unlock_exit:
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mutex_unlock(&priv->reg_mutex);
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}
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+/* On page 205, section "8.6.3 Frame filtering" of the active standard, IEEE Std
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+ * 802.1Q™-2022, it is stated that frames with 01:80:C2:00:00:00-0F as MAC DA
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+ * must only be propagated to C-VLAN and MAC Bridge components. That means
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+ * VLAN-aware and VLAN-unaware bridges. On the switch designs with CPU ports,
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+ * these frames are supposed to be processed by the CPU (software). So we make
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+ * the switch only forward them to the CPU port. And if received from a CPU
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+ * port, forward to a single port. The software is responsible of making the
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+ * switch conform to the latter by setting a single port as destination port on
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+ * the special tag.
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+ *
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+ * This switch intellectual property cannot conform to this part of the standard
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+ * fully. Whilst the REV_UN frame tag covers the remaining :04-0D and :0F MAC
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+ * DAs, it also includes :22-FF which the scope of propagation is not supposed
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+ * to be restricted for these MAC DAs.
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+ */
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static void
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mt753x_trap_frames(struct mt7530_priv *priv)
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{
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@@ -1012,13 +1027,27 @@ mt753x_trap_frames(struct mt7530_priv *p
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MT753X_BPDU_EG_TAG(MT7530_VLAN_EG_UNTAGGED) |
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MT753X_BPDU_CPU_ONLY);
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- /* Trap LLDP frames with :0E MAC DA to the CPU port(s) and egress them
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- * VLAN-untagged.
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+ /* Trap frames with :01 and :02 MAC DAs to the CPU port(s) and egress
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+ * them VLAN-untagged.
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+ */
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+ mt7530_rmw(priv, MT753X_RGAC1, MT753X_R02_EG_TAG_MASK |
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+ MT753X_R02_PORT_FW_MASK | MT753X_R01_EG_TAG_MASK |
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+ MT753X_R01_PORT_FW_MASK,
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+ MT753X_R02_EG_TAG(MT7530_VLAN_EG_UNTAGGED) |
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+ MT753X_R02_PORT_FW(MT753X_BPDU_CPU_ONLY) |
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+ MT753X_R01_EG_TAG(MT7530_VLAN_EG_UNTAGGED) |
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+ MT753X_BPDU_CPU_ONLY);
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+
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+ /* Trap frames with :03 and :0E MAC DAs to the CPU port(s) and egress
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+ * them VLAN-untagged.
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*/
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mt7530_rmw(priv, MT753X_RGAC2, MT753X_R0E_EG_TAG_MASK |
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- MT753X_R0E_PORT_FW_MASK,
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+ MT753X_R0E_PORT_FW_MASK | MT753X_R03_EG_TAG_MASK |
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+ MT753X_R03_PORT_FW_MASK,
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MT753X_R0E_EG_TAG(MT7530_VLAN_EG_UNTAGGED) |
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- MT753X_R0E_PORT_FW(MT753X_BPDU_CPU_ONLY));
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+ MT753X_R0E_PORT_FW(MT753X_BPDU_CPU_ONLY) |
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+ MT753X_R03_EG_TAG(MT7530_VLAN_EG_UNTAGGED) |
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+ MT753X_BPDU_CPU_ONLY);
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}
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static int
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--- a/drivers/net/dsa/mt7530.h
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+++ b/drivers/net/dsa/mt7530.h
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@@ -71,12 +71,25 @@ enum mt753x_id {
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#define MT753X_BPDU_EG_TAG(x) FIELD_PREP(MT753X_BPDU_EG_TAG_MASK, x)
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#define MT753X_BPDU_PORT_FW_MASK GENMASK(2, 0)
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+/* Register for :01 and :02 MAC DA frame control */
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+#define MT753X_RGAC1 0x28
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+#define MT753X_R02_EG_TAG_MASK GENMASK(24, 22)
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+#define MT753X_R02_EG_TAG(x) FIELD_PREP(MT753X_R02_EG_TAG_MASK, x)
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+#define MT753X_R02_PORT_FW_MASK GENMASK(18, 16)
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+#define MT753X_R02_PORT_FW(x) FIELD_PREP(MT753X_R02_PORT_FW_MASK, x)
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+#define MT753X_R01_EG_TAG_MASK GENMASK(8, 6)
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+#define MT753X_R01_EG_TAG(x) FIELD_PREP(MT753X_R01_EG_TAG_MASK, x)
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+#define MT753X_R01_PORT_FW_MASK GENMASK(2, 0)
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+
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/* Register for :03 and :0E MAC DA frame control */
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#define MT753X_RGAC2 0x2c
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#define MT753X_R0E_EG_TAG_MASK GENMASK(24, 22)
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#define MT753X_R0E_EG_TAG(x) FIELD_PREP(MT753X_R0E_EG_TAG_MASK, x)
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#define MT753X_R0E_PORT_FW_MASK GENMASK(18, 16)
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#define MT753X_R0E_PORT_FW(x) FIELD_PREP(MT753X_R0E_PORT_FW_MASK, x)
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+#define MT753X_R03_EG_TAG_MASK GENMASK(8, 6)
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+#define MT753X_R03_EG_TAG(x) FIELD_PREP(MT753X_R03_EG_TAG_MASK, x)
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+#define MT753X_R03_PORT_FW_MASK GENMASK(2, 0)
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enum mt753x_bpdu_port_fw {
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MT753X_BPDU_FOLLOW_MFC,
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