92 lines
2.9 KiB
C
92 lines
2.9 KiB
C
#include <common.h>
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#include <asm/arch/sysctl.h>
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#include <asm/arch/pinmux.h>
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#include <asm/arch/clock.h>
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void reset_cpu(ulong addr)
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{
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u32 value;
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// Assert reset to cores as per power on defaults
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// Don't touch the DDR interface as things will come to an impromptu stop
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// NB Possibly should be asserting reset for PLLB, but there are timing
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// concerns here according to the docs
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value =
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BIT(SYS_CTRL_RST_COPRO ) |
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BIT(SYS_CTRL_RST_USBHS ) |
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BIT(SYS_CTRL_RST_USBHSPHYA ) |
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BIT(SYS_CTRL_RST_MACA ) |
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BIT(SYS_CTRL_RST_PCIEA ) |
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BIT(SYS_CTRL_RST_SGDMA ) |
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BIT(SYS_CTRL_RST_CIPHER ) |
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BIT(SYS_CTRL_RST_SATA ) |
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BIT(SYS_CTRL_RST_SATA_LINK ) |
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BIT(SYS_CTRL_RST_SATA_PHY ) |
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BIT(SYS_CTRL_RST_PCIEPHY ) |
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BIT(SYS_CTRL_RST_STATIC ) |
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BIT(SYS_CTRL_RST_UART1 ) |
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BIT(SYS_CTRL_RST_UART2 ) |
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BIT(SYS_CTRL_RST_MISC ) |
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BIT(SYS_CTRL_RST_I2S ) |
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BIT(SYS_CTRL_RST_SD ) |
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BIT(SYS_CTRL_RST_MACB ) |
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BIT(SYS_CTRL_RST_PCIEB ) |
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BIT(SYS_CTRL_RST_VIDEO ) |
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BIT(SYS_CTRL_RST_USBHSPHYB ) |
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BIT(SYS_CTRL_RST_USBDEV );
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writel(value, SYS_CTRL_RST_SET_CTRL);
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// Release reset to cores as per power on defaults
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writel(BIT(SYS_CTRL_RST_GPIO), SYS_CTRL_RST_CLR_CTRL);
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// Disable clocks to cores as per power-on defaults - must leave DDR
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// related clocks enabled otherwise we'll stop rather abruptly.
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value =
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BIT(SYS_CTRL_CLK_COPRO) |
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BIT(SYS_CTRL_CLK_DMA) |
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BIT(SYS_CTRL_CLK_CIPHER) |
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BIT(SYS_CTRL_CLK_SD) |
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BIT(SYS_CTRL_CLK_SATA) |
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BIT(SYS_CTRL_CLK_I2S) |
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BIT(SYS_CTRL_CLK_USBHS) |
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BIT(SYS_CTRL_CLK_MAC) |
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BIT(SYS_CTRL_CLK_PCIEA) |
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BIT(SYS_CTRL_CLK_STATIC) |
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BIT(SYS_CTRL_CLK_MACB) |
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BIT(SYS_CTRL_CLK_PCIEB) |
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BIT(SYS_CTRL_CLK_REF600) |
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BIT(SYS_CTRL_CLK_USBDEV);
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writel(value, SYS_CTRL_CLK_CLR_CTRL);
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// Enable clocks to cores as per power-on defaults
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// Set sys-control pin mux'ing as per power-on defaults
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writel(0, SYS_CONTROL_BASE + PINMUX_SECONDARY_SEL);
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writel(0, SYS_CONTROL_BASE + PINMUX_TERTIARY_SEL);
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writel(0, SYS_CONTROL_BASE + PINMUX_QUATERNARY_SEL);
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writel(0, SYS_CONTROL_BASE + PINMUX_DEBUG_SEL);
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writel(0, SYS_CONTROL_BASE + PINMUX_ALTERNATIVE_SEL);
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writel(0, SYS_CONTROL_BASE + PINMUX_PULLUP_SEL);
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writel(0, SEC_CONTROL_BASE + PINMUX_SECONDARY_SEL);
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writel(0, SEC_CONTROL_BASE + PINMUX_TERTIARY_SEL);
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writel(0, SEC_CONTROL_BASE + PINMUX_QUATERNARY_SEL);
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writel(0, SEC_CONTROL_BASE + PINMUX_DEBUG_SEL);
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writel(0, SEC_CONTROL_BASE + PINMUX_ALTERNATIVE_SEL);
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writel(0, SEC_CONTROL_BASE + PINMUX_PULLUP_SEL);
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// No need to save any state, as the ROM loader can determine whether reset
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// is due to power cycling or programatic action, just hit the (self-
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// clearing) CPU reset bit of the block reset register
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value =
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BIT(SYS_CTRL_RST_SCU) |
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BIT(SYS_CTRL_RST_ARM0) |
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BIT(SYS_CTRL_RST_ARM1);
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writel(value, SYS_CTRL_RST_SET_CTRL);
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}
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