133 lines
4.1 KiB
Diff
133 lines
4.1 KiB
Diff
From d637252f72998261c9d77c0be57317c73ad77f83 Mon Sep 17 00:00:00 2001
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From: Laurentiu Tudor <laurentiu.tudor@nxp.com>
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Date: Tue, 26 Jul 2016 16:38:18 +0300
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Subject: [PATCH] arm/arm64: KVM: drop qman mmio cacheable mapping hack
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Instead of hardcoding checks for qman cacheable
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mmio region physical addresses extract mapping
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information from the user-space mapping.
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The involves several steps;
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- get access to a pte part of the user-space mapping
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by using get_locked_pte() / pte_unmap_unlock() apis
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- extract memtype (normal / device), shareability from
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the pte
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- convert to S2 translation bits in newly added
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function stage1_to_stage2_pgprot()
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- finish making the s2 translation with the obtained bits
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Another explored option was using vm_area_struct::vm_page_prot
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which is set in vfio-mc mmap code to the correct page bits.
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However, experiments show that these bits are later altered
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in the generic mmap code (e.g. the shareability bit is always
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set on arm64).
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The only place where the original bits can still be found
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is the user-space mapping, using the method described above.
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Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com>
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[Bharat - Fixed mem_type check issue]
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[changed "ifdef ARM64" to CONFIG_ARM64]
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Signed-off-by: Bharat Bhushan <Bharat.Bhushan@nxp.com>
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[Ioana - added a sanity check for hugepages]
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Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
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[Fixed format issues]
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Signed-off-by: Diana Craciun <diana.craciun@nxp.com>
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---
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virt/kvm/arm/mmu.c | 55 ++++++++++++++++++++++++++++++++++++++++++++++++++++--
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1 file changed, 53 insertions(+), 2 deletions(-)
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--- a/virt/kvm/arm/mmu.c
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+++ b/virt/kvm/arm/mmu.c
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@@ -1381,6 +1381,30 @@ out:
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return ret;
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}
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+#ifdef CONFIG_ARM64
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+static pgprot_t stage1_to_stage2_pgprot(pgprot_t prot)
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+{
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+ switch (pgprot_val(prot) & PTE_ATTRINDX_MASK) {
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+ case PTE_ATTRINDX(MT_DEVICE_nGnRE):
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+ case PTE_ATTRINDX(MT_DEVICE_nGnRnE):
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+ case PTE_ATTRINDX(MT_DEVICE_GRE):
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+ return PAGE_S2_DEVICE;
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+ case PTE_ATTRINDX(MT_NORMAL_NC):
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+ case PTE_ATTRINDX(MT_NORMAL):
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+ return (pgprot_val(prot) & PTE_SHARED)
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+ ? PAGE_S2
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+ : PAGE_S2_NS;
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+ }
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+
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+ return PAGE_S2_DEVICE;
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+}
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+#else
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+static pgprot_t stage1_to_stage2_pgprot(pgprot_t prot)
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+{
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+ return PAGE_S2_DEVICE;
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+}
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+#endif
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+
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static bool transparent_hugepage_adjust(kvm_pfn_t *pfnp, phys_addr_t *ipap)
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{
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kvm_pfn_t pfn = *pfnp;
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@@ -1725,8 +1749,23 @@ static int user_mem_abort(struct kvm_vcp
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* 3 levels, i.e, PMD is not folded.
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*/
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if (vma_pagesize == PMD_SIZE ||
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- (vma_pagesize == PUD_SIZE && kvm_stage2_has_pmd(kvm)))
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+ (vma_pagesize == PUD_SIZE && kvm_stage2_has_pmd(kvm))) {
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gfn = (fault_ipa & huge_page_mask(hstate_vma(vma))) >> PAGE_SHIFT;
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+ } else {
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+ if (!is_vm_hugetlb_page(vma)) {
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+ pte_t *pte;
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+ spinlock_t *ptl;
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+ pgprot_t prot;
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+
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+ pte = get_locked_pte(current->mm, memslot->userspace_addr, &ptl);
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+ prot = stage1_to_stage2_pgprot(__pgprot(pte_val(*pte)));
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+ pte_unmap_unlock(pte, ptl);
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+#ifdef CONFIG_ARM64
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+ if (pgprot_val(prot) == pgprot_val(PAGE_S2_NS))
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+ mem_type = PAGE_S2_NS;
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+#endif
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+ }
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+ }
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up_read(¤t->mm->mmap_sem);
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/* We need minimum second+third level pages */
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@@ -1755,6 +1794,11 @@ static int user_mem_abort(struct kvm_vcp
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if (is_error_noslot_pfn(pfn))
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return -EFAULT;
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+#ifdef CONFIG_ARM64
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+ if (pgprot_val(mem_type) == pgprot_val(PAGE_S2_NS)) {
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+ flags |= KVM_S2PTE_FLAG_IS_IOMAP;
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+ } else
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+#endif
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if (kvm_is_device_pfn(pfn)) {
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mem_type = PAGE_S2_DEVICE;
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flags |= KVM_S2PTE_FLAG_IS_IOMAP;
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@@ -2352,6 +2396,9 @@ int kvm_arch_prepare_memory_region(struc
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gpa_t gpa = mem->guest_phys_addr +
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(vm_start - mem->userspace_addr);
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phys_addr_t pa;
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+ pgprot_t prot;
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+ pte_t *pte;
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+ spinlock_t *ptl;
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pa = (phys_addr_t)vma->vm_pgoff << PAGE_SHIFT;
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pa += vm_start - vma->vm_start;
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@@ -2362,9 +2409,13 @@ int kvm_arch_prepare_memory_region(struc
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goto out;
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}
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+ pte = get_locked_pte(current->mm, mem->userspace_addr, &ptl);
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+ prot = stage1_to_stage2_pgprot(__pgprot(pte_val(*pte)));
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+ pte_unmap_unlock(pte, ptl);
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+
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ret = kvm_phys_addr_ioremap(kvm, gpa, pa,
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vm_end - vm_start,
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- writable, PAGE_S2_DEVICE);
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+ writable, prot);
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if (ret)
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break;
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}
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