82 lines
2.7 KiB
Diff
82 lines
2.7 KiB
Diff
From 5b08c1d567ee8e6af94696b3e549997cbdb2bb80 Mon Sep 17 00:00:00 2001
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From: Jaiganesh Narayanan <njaigane@codeaurora.org>
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Date: Thu, 1 Sep 2016 10:40:38 +0530
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Subject: [PATCH] pinctrl: qcom: ipq4019: add open drain support
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Signed-off-by: Jaiganesh Narayanan <njaigane@codeaurora.org>
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[ Brian: adapted from from the Chromium OS kernel used on IPQ4019-based
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WiFi APs. ]
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Signed-off-by: Brian Norris <computersforpeace@gmail.com>
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---
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https://lore.kernel.org/linux-gpio/20200703080646.23233-1-computersforpeace@gmail.com/
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drivers/pinctrl/qcom/pinctrl-ipq4019.c | 1 +
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drivers/pinctrl/qcom/pinctrl-msm.c | 13 +++++++++++++
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drivers/pinctrl/qcom/pinctrl-msm.h | 2 ++
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3 files changed, 16 insertions(+)
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--- a/drivers/pinctrl/qcom/pinctrl-ipq4019.c
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+++ b/drivers/pinctrl/qcom/pinctrl-ipq4019.c
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@@ -254,6 +254,7 @@ DECLARE_QCA_GPIO_PINS(99);
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.mux_bit = 2, \
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.pull_bit = 0, \
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.drv_bit = 6, \
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+ .od_bit = 12, \
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.oe_bit = 9, \
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.in_bit = 0, \
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.out_bit = 1, \
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--- a/drivers/pinctrl/qcom/pinctrl-msm.c
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+++ b/drivers/pinctrl/qcom/pinctrl-msm.c
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@@ -225,6 +225,10 @@ static int msm_config_reg(struct msm_pin
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*bit = g->pull_bit;
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*mask = 3;
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break;
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+ case PIN_CONFIG_DRIVE_OPEN_DRAIN:
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+ *bit = g->od_bit;
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+ *mask = 1;
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+ break;
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case PIN_CONFIG_DRIVE_STRENGTH:
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*bit = g->drv_bit;
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*mask = 7;
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@@ -302,6 +306,12 @@ static int msm_config_group_get(struct p
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if (!arg)
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return -EINVAL;
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break;
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+ case PIN_CONFIG_DRIVE_OPEN_DRAIN:
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+ /* Pin is not open-drain */
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+ if (!arg)
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+ return -EINVAL;
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+ arg = 1;
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+ break;
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case PIN_CONFIG_DRIVE_STRENGTH:
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arg = msm_regval_to_drive(arg);
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break;
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@@ -374,6 +384,9 @@ static int msm_config_group_set(struct p
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else
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arg = MSM_PULL_UP;
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break;
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+ case PIN_CONFIG_DRIVE_OPEN_DRAIN:
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+ arg = 1;
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+ break;
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case PIN_CONFIG_DRIVE_STRENGTH:
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/* Check for invalid values */
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if (arg > 16 || arg < 2 || (arg % 2) != 0)
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--- a/drivers/pinctrl/qcom/pinctrl-msm.h
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+++ b/drivers/pinctrl/qcom/pinctrl-msm.h
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@@ -38,6 +38,7 @@ struct msm_function {
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* @mux_bit: Offset in @ctl_reg for the pinmux function selection.
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* @pull_bit: Offset in @ctl_reg for the bias configuration.
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* @drv_bit: Offset in @ctl_reg for the drive strength configuration.
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+ * @od_bit: Offset in @ctl_reg for controlling open drain.
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* @oe_bit: Offset in @ctl_reg for controlling output enable.
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* @in_bit: Offset in @io_reg for the input bit value.
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* @out_bit: Offset in @io_reg for the output bit value.
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@@ -75,6 +76,7 @@ struct msm_pingroup {
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unsigned pull_bit:5;
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unsigned drv_bit:5;
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+ unsigned od_bit:5;
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unsigned oe_bit:5;
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unsigned in_bit:5;
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unsigned out_bit:5;
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